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88ALP01
PCI to NAND, SD and Camera Host Controller
Datasheet
Doc. No. MV-S103921-00, Rev. - July 17, 2007 Marvell. Moving Forward Faster Document Classification: Proprietary Information
88ALP01 Datasheet
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Doc. No. MV-S103921-00 Rev. - Page 2 Document Classification: Proprietary Information
Copyright (c) 2007 Marvell July 17, 2007, Preliminary
88ALP01
PCI to NAND, SD and Camera Host Controller
Datasheet
PRODUCT OVERVIEW
Overview
The Marvell(R) single-chip 88ALP01 triple function device integrates a NAND flash controller (with Reed-Solomon ECC), an SD/SDIO controller, and a CMOS Camera Module Interface Controller (CCIC). The device is ideally suited for laptop computing devices and other embedded applications. The 88ALP01 package is optimized for 32-bit PCI clients. The small 128-pin TQFP package with low pin count minimizes board space, simplifies signal routing, and reduces the number of required PCB layers, resulting in cost-effective motherboard and low profile system implementations. The 88ALP01 is optimized for maximum throughput and low PCI Bus and CPU utilization. Adequate on-chip memory buffers enable efficient PCI bus cycles and data buffering and eliminates the need for external memory. Direct Memory Address (DMA)-based burst data transfer reduces CPU and PCI bus utilization and improves overall system performance.
Standard camera interface controller Each function operating independently: - Dedicated driver
- -
SD/SDIO controller
Separated controls All functions have host interrupt capability Interrupts OR together and sent to INTAn On-chip generated power-on reset NAND Flash controller supports both DMA and PIO modes SD controller supports DMA and PIO modes Camera interface controller supports DMA data transfer
- - -
Separated configuration registers Separated buffers
NAND Controller
Configurable to interface with different 8-bit NAND Flash devices (Samsung and Toshiba) Supports either 512 byte or 2 KB page sizes Configurable to work with different single chip NAND Flash sizes from 128 Mbit to 64 Gbit Basic NAND Flash functions: - Page program/read
General Features
PCI Interface
Fully compliant with PCI v2.3, 32-bit, 33 MHz
Note
66 MHz support is pending final analysis of PCI timing.
Programmable cache line size 3.3V signalling PCI Bus master Burst transfer Supports DMA and PIO operations Supports PCI power states Supports three functions in a chip: - NAND Flash Controller
Reset and lock Supports hardware ECC (Reed-Solomon algorithm) - 4 bit-symbol detection and correction
- - - - -
Block erase Random program/read ID read Status read
-
12-bit per symbol with data automatic packing
SD/SDIO
Supports 1-bit/4-bit SD, SDIO cards Up to 48 MHz for SD Supports interrupts for information exchange between host and cards
Copyright (c) 2007 Marvell July 17, 2007, Preliminary Document Classification: Proprietary Information
Doc. No. MV-S103921-00 Rev. - Page 3
88ALP01 Datasheet
Supports read wait commands in SD cards Hardware Cyclic Redundancy Check (CRC) generating and checking Supports DMA and PIO operations Suspend and resume in SDIO cards
Camera Interface
Supports high-resolution CMOS camera module Supports both RGB and YUV formats Standard 8-wire camera interfaces DMA pixel data transfer Host interrupt capability Supports programmable pixel clock
Note
Only SDMEM card has been tested at this time.
Package
14mm x 14mm, 128 TQFP (EPAD) Lead-free package available
Doc. No. MV-S103921-00 Rev. - Page 4 Document Classification: Proprietary Information
Copyright (c) 2007 Marvell July 17, 2007, Preliminary
Table of Contents
Table of Contents
Product Overview ....................................................................................................................................... 3 1
1.1 1.2 1.3
Signal Description ....................................................................................................................... 21
Signal Diagram................................................................................................................................................21 128-Pin TQFP Package ..................................................................................................................................22 Pin Description ................................................................................................................................................23
2
2.1
Functional Description................................................................................................................ 29
System Overview ............................................................................................................................................29 2.1.1 System Component Description .......................................................................................................29 2.1.1.1 Power Supplies ..................................................................................................................29 2.1.1.2 External Reference Clock...................................................................................................30 2.1.1.3 External TWSI EEPROM (VPD) .........................................................................................30 Functional Overview........................................................................................................................................30 2.2.1 PCI Bus Interface Unit ......................................................................................................................30 2.2.1.1 Slave Access to Configuration Space ................................................................................31 2.2.1.2 Slave Access to Memory Resources..................................................................................31 2.2.1.3 Master Access ....................................................................................................................31 2.2.1.4 Parity Generation/Check ....................................................................................................32 2.2.2 NAND Flash Controller .....................................................................................................................33 2.2.2.1 Write Operations ................................................................................................................33 2.2.2.2 Read Operations ................................................................................................................33 2.2.3 SDIO Host Controller ........................................................................................................................38 2.2.3.1 Features .............................................................................................................................39 2.2.3.2 SD Bus Protocol Description ..............................................................................................39 2.2.3.3 Special Bus Transactions ...................................................................................................40 2.2.3.4 Card Detection ...................................................................................................................44 2.2.4 CMOS Camera Interface Controller..................................................................................................45 2.2.4.1 Features .............................................................................................................................45 2.2.4.2 I/O Signals..........................................................................................................................45 2.2.4.3 Interface Modes..................................................................................................................46 2.2.4.4 Input/Output Matrix .............................................................................................................47 2.2.4.5 Video Timing Reference Codes (SAV and EAV)................................................................47 2.2.4.6 RGB Input Data Formats ....................................................................................................48 2.2.4.7 CCIC Recommended Programming Sequence .................................................................49 2.2.5 VPD Serial EEPROM........................................................................................................................49 2.2.5.1 VPD Serial EEPROM Loader .............................................................................................50 2.2.5.2 VPD Two-Wire Serial Interface ..........................................................................................51 2.2.6 Device Reset ....................................................................................................................................52 2.2.7 Reset Configuration ..........................................................................................................................52 2.2.8 Clock Generation/Distribution ...........................................................................................................52 2.2.9 PME on Wake up event ....................................................................................................................52 2.2.9.1 Power Management Support..............................................................................................53 2.2.9.2 PCI Device Power States ...................................................................................................53 2.2.9.3 Wake-Up Sequence ...........................................................................................................53 2.2.10 Clock Run (CLK_RUNn) ...................................................................................................................54 2.2.11 Power on Reset Delay ......................................................................................................................54
2.2
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88ALP01 Datasheet
3
3.1 3.2
Register Description ................................................................................................................... 55
Registers Introduction .....................................................................................................................................55 3.1.1 Register Conventions .......................................................................................................................55 PCI Configuration Register File.......................................................................................................................56 3.2.1 Configuration Data Access ...............................................................................................................56 3.2.2 PCI Header Region...........................................................................................................................57 3.2.2.1 Vendor ID Register .............................................................................................................60 3.2.2.2 Device ID Register .............................................................................................................60 3.2.2.3 Command Register ............................................................................................................60 3.2.2.4 Status Register ...................................................................................................................62 3.2.2.5 Revision ID Register...........................................................................................................63 3.2.2.6 Class Code Register ..........................................................................................................63 3.2.2.7 Cache Line Register ...........................................................................................................64 3.2.2.8 Latency Timer Register ......................................................................................................64 3.2.2.9 Header Type Register ........................................................................................................65 3.2.2.10 Built-in Self Test Register ...................................................................................................65 3.2.2.11 Base Address Register (1st) ..............................................................................................65 3.2.2.12 Subsystem Vendor ID Register ..........................................................................................66 3.2.2.13 Subsystem ID Register.......................................................................................................66 3.2.2.14 New Capabilities Pointer ....................................................................................................67 3.2.2.15 Interrupt Line Register ........................................................................................................67 3.2.2.16 Interrupt Pin Register .........................................................................................................67 3.2.2.17 Min_Gnt Register ...............................................................................................................68 3.2.2.18 Max_Lat Register ...............................................................................................................68 3.2.2.19 Expansion ROM Base Address Register ...........................................................................68 3.2.3 Device Dependent Region ................................................................................................................68 3.2.3.1 SD Slot Information Register ..............................................................................................69 3.2.3.2 Access Control and VPD Control Registers .......................................................................69 3.2.3.3 Power Management Capability ID Register .......................................................................71 3.2.3.4 Power Management Next Item Pointer ..............................................................................71 3.2.3.5 Power Management Capabilities Register .........................................................................72 3.2.3.6 Power Management Control/Status Register .....................................................................73 3.2.3.7 Power Management Data Register ....................................................................................74 3.2.3.8 Power Management Data Table.........................................................................................74 3.2.3.9 VPD Capability ID Register ................................................................................................75 3.2.3.10 VPD Next Item Pointer .......................................................................................................75 3.2.3.11 VPD Address Register .......................................................................................................75 3.2.3.12 VPD Data Register .............................................................................................................76 3.2.3.13 VPD Serial EEPROM Loader Control Register ..................................................................76 3.2.3.14 MSI Capability ID Register (MSI Cap ID) ...........................................................................76 3.2.3.15 MSI Next Item Pointer ........................................................................................................77 3.2.3.16 MSI Message Control .........................................................................................................77 3.2.3.17 MSI Message Address .......................................................................................................78 3.2.3.18 MSI Message Data .............................................................................................................79 3.2.3.19 Calibration Control Register ...............................................................................................79 3.2.3.20 Calibration Status Register.................................................................................................80 3.2.3.21 Discard Counter Register ...................................................................................................80 3.2.3.22 Retry Counter Register.......................................................................................................80 Global Control Registers .................................................................................................................................81 3.3.1 Register Map ....................................................................................................................................81 3.3.2 Register Descriptions........................................................................................................................81 3.3.2.1 Control/Status.....................................................................................................................81 3.3.2.2 Interrupt Source Register ...................................................................................................83 3.3.2.3 Interrupt Mask Register ......................................................................................................83
3.3
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Table of Contents
3.3.2.4 3.3.2.5 3.3.2.6 3.3.2.7 3.3.2.8 3.3.2.9 3.3.2.10 3.3.2.11 3.3.2.12 3.4
Interrupt HW Error Source Register ...................................................................................84 Interrupt HW Error Mask Register ......................................................................................85 PLL Control Register ..........................................................................................................85 Block Control Register........................................................................................................86 GPIO Functional Control Register ......................................................................................86 Test Control Register .........................................................................................................87 General Purpose I/O Register ............................................................................................87 VPD TWSI (HW) Registers ................................................................................................88 VPD TWSI (SW) Register ..................................................................................................89
NAND Flash Unit .............................................................................................................................................90 3.4.1 Register Map ....................................................................................................................................90 3.4.2 Registers...........................................................................................................................................91 SDIO Host Controller Registers ....................................................................................................................101 3.5.1 Register Map ..................................................................................................................................101 CMOS Camera Interface Controller ..............................................................................................................124 3.6.1 Register Map ..................................................................................................................................124 3.6.2 Register Descriptions......................................................................................................................125
3.5 3.6
4 5
5.1 5.2 5.3 5.4
Mechanical Drawings ................................................................................................................140 Electrical Specifications ...........................................................................................................141
Absolute Maximum Ratings ..........................................................................................................................141 Recommended Operating Conditions ...........................................................................................................141 Package Thermal Conditions ........................................................................................................................142 DC Electrical Characteristics.........................................................................................................................142 5.4.1 Current Consumption AVDD_PLL ..................................................................................................142 5.4.2 Current Consumption VDD .............................................................................................................143 5.4.3 Current Consumption VDDO ..........................................................................................................143 5.4.4 Current Consumption VDDOC........................................................................................................143 Input Clock Specifications .............................................................................................................................143 Internal Resistors ..........................................................................................................................................144 PCI Bus Interface Unit...................................................................................................................................144 5.7.1 DC Electricals .................................................................................................................................144 5.7.2 AC Electricals .................................................................................................................................145 5.7.3 Protocol Timing ...............................................................................................................................145 NAND Flash Controller..................................................................................................................................146 5.8.1 DC Electricals .................................................................................................................................146 5.8.2 Protocol Timing ...............................................................................................................................146 SDIO .............................................................................................................................................................149 5.9.1 DC Electricals .................................................................................................................................149 5.9.2 Protocol Timing ...............................................................................................................................150 CMOS Camera Interface...............................................................................................................................152 5.10.1 DC Electricals .................................................................................................................................152 5.10.2 Protocol Timing ...............................................................................................................................152 JTAG Test Interface ......................................................................................................................................153 5.11.1 DC Electricals .................................................................................................................................153 5.11.2 Protocol Timing ...............................................................................................................................154 GPIO .............................................................................................................................................................155 5.12.1 DC Electricals .................................................................................................................................155 5.12.2 LED Mode .......................................................................................................................................155
5.5 5.6 5.7
5.8
5.9
5.10
5.11
5.12
Copyright (c) 2007 Marvell July 17, 2007, Preliminary Document Classification: Proprietary Information
Doc. No. MV-S103921-00 Rev. - Page 7
88ALP01 Datasheet
6
6.1 6.2
Part Order Numbering/Package Marking ................................................................................156
Part Order Numbering ...................................................................................................................................156 Package Marking ..........................................................................................................................................157
A
Acronyms and Abbreviations...................................................................................................158
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Copyright (c) 2007 Marvell July 17, 2007, Preliminary
List of Tables
List of Tables
1
1.1 1.2 1.3
Signal Description ............................................................................................................................ 21
Signal Diagram................................................................................................................................................21 128-Pin TQFP Package ..................................................................................................................................22 Pin Description ................................................................................................................................................23 Table 1: Table 2: Table 3: Table 4: Table 5: Table 6: Table 7: Table 8: Table 9: Table 10: Table 11: Pin Type Definitions ..........................................................................................................................23 SD/SDIO Interface (3.3V) .................................................................................................................23 PCI Interface (3.3V) ..........................................................................................................................24 NAND Flash (3.3V) ...........................................................................................................................25 Camera Interface (2.5 or 3.3V) .........................................................................................................26 VPD TWSI (Serial EEPROM, 3.3V) ..................................................................................................26 Main Clock Interface (PLL, 3.3V) ......................................................................................................27 GPIO Interface (3.3V) .......................................................................................................................27 Joint Test Action Group (JTAG) and Test Interface (3.3V) ...............................................................27 Core VDD Control (1.2V) ..................................................................................................................28 Power and Ground............................................................................................................................28
2
2.1 2.2
Functional Description..................................................................................................................... 29
System Overview ............................................................................................................................................29 Functional Overview........................................................................................................................................30 Table 12: Table 13: Table 14: Table 15: Table 16: Table 17: Table 18: Table 19: Table 20: Table 21: Table 22: Table 23: Samsung Type 1 NAND Flash Device Command Sets and Support ...............................................35 Samsung Type 2 NAND Flash Device Command Sets and Support ...............................................35 CCIC Chip-Level I/O Signal Descriptions (2.5V or 3.3V) ..................................................................45 Supported Interface Modes ..............................................................................................................46 Color I/O Matrix.................................................................................................................................47 Video Timing Reference Codes ........................................................................................................47 Bits States ........................................................................................................................................47 8-bit RGB 5:6:5 Input Data Format ...................................................................................................48 8-bit YCbCr 4:2:2 Input Data Format ................................................................................................48 Data Format of First 8 byte Block within Serial EEPROM ................................................................51 88ALP01 Configuration Pins.............................................................................................................52 Device Power Status ........................................................................................................................53
3
3.1 3.2
Register Description......................................................................................................................... 55
Registers Introduction .....................................................................................................................................55 Table 24: Table 25: Table 26: Table 55: Register Type Definitions..................................................................................................................55 PCI Header Region Overview...........................................................................................................57 PCI Header Region Register Map ....................................................................................................58 Power Management Data Table .......................................................................................................74 PCI Configuration Register File.......................................................................................................................56
3.3
Global Control Registers .................................................................................................................................81
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Doc. No. MV-S103921-00 Rev. - Page 9
88ALP01 Datasheet
Table 71: 3.4 3.5 3.6 Table 86:
Global Control Register Map ............................................................................................................81 NAND Flash Unit Registers ..............................................................................................................90
NAND Flash Unit .............................................................................................................................................90 SDIO Host Controller Registers ....................................................................................................................101 Table 114: SDIO Host Controller Register Map................................................................................................101 CMOS Camera Interface Controller ..............................................................................................................124 Table 159: CMOS Camera Interface Controller Register Map .........................................................................124
4 5
5.1 5.2 5.3 5.4
Mechanical Drawings .....................................................................................................................140 Electrical Specifications ................................................................................................................141
Absolute Maximum Ratings ..........................................................................................................................141 Table 183: Absolute Maximum Ratings ............................................................................................................141 Recommended Operating Conditions ...........................................................................................................141 Table 184: Recommended Operating Conditions.............................................................................................141 Package Thermal Conditions ........................................................................................................................142 Table 185: 14 x 14 mm TQFP Package ...........................................................................................................142 DC Electrical Characteristics.........................................................................................................................142 Table 186: Current Consumption AVDD_PLL ..................................................................................................142 Table 187: Current Consumption VDD .............................................................................................................143 Table 188: Current Consumption VDDO ..........................................................................................................143 Table 189: Current Consumption VDDOC........................................................................................................143
5.5 5.6 5.7
Input Clock Specifications .............................................................................................................................143 Table 190: 24 MHz Reference Clock Timing ....................................................................................................143 Internal Resistors ..........................................................................................................................................144 Table 191: Internal Resistors ............................................................................................................................144 PCI Bus Interface Unit...................................................................................................................................144 Table 192: PCI Bus Interface Unit DC Specifications .......................................................................................144 Table 193: PCI Bus Interface Unit AC Specifications .......................................................................................145 Table 194: 66 and 33 MHz PCI Timing.............................................................................................................145
5.8
NAND Flash Controller..................................................................................................................................146 Table 195: NAND Flash DC Specifications ......................................................................................................146 Table 196: NAND Flash Timing ........................................................................................................................148
5.9
SDIO .............................................................................................................................................................149 Table 197: SDIO DC Specifications..................................................................................................................149 Table 198: SDIO Low Speed Timing ................................................................................................................150 Table 199: SDIO High Speed Timing ...............................................................................................................151
5.10
CMOS Camera Interface...............................................................................................................................152 Table 200: CMOS Camera Interface DC Specifications ...................................................................................152 Table 201: CMOS Camera Timing ...................................................................................................................153
5.11
JTAG Test Interface ......................................................................................................................................153 Table 202: JTAG Test Interface DC Specifications for 3.3V Signaling .............................................................153 Table 203: JTAG Timing ...................................................................................................................................154
5.12
GPIO .............................................................................................................................................................155
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Copyright (c) 2007 Marvell July 17, 2007, Preliminary
List of Tables
Table 204: GPIO DC Specifications for 3.3V Signaling ....................................................................................155 Table 205: LED Mode .......................................................................................................................................155
6
6.1 6.2
Part Order Numbering/Package Marking......................................................................................156
Part Order Numbering ...................................................................................................................................156 Table 206: 88ALP01 Part Order Options ..........................................................................................................156 Package Marking ..........................................................................................................................................157 Table 207: Acronyms and Abbreviations ..........................................................................................................158
Copyright (c) 2007 Marvell July 17, 2007, Preliminary Document Classification: Proprietary Information
Doc. No. MV-S103921-00 Rev. - Page 11
88ALP01 Datasheet
List of Figures
1
1.1 1.2 1.3
Signal Description ........................................................................................................................... 21
Signal Diagram................................................................................................................................................21 Figure 1: Figure 2: Signal Diagram .................................................................................................................................21 TQFP Pinout .....................................................................................................................................22 128-Pin TQFP Package ..................................................................................................................................22 Pin Description ................................................................................................................................................23
2
2.1 2.2
Functional Description.................................................................................................................... 29
System Overview ............................................................................................................................................29 Figure 3: Figure 4: Figure 5: Figure 6: Figure 7: Figure 8: Figure 9: Figure 10: Figure 11: Figure 12: Figure 13: Figure 14: Figure 15: Figure 16: Figure 17: Figure 18: Figure 19: 88ALP01 System Diagram ...............................................................................................................29 88ALP01 Functional Block Diagram .................................................................................................30 NAND Flash Controller Block Diagram ............................................................................................34 NAND Flash .....................................................................................................................................34 Reed-Solomon ECC Diagram ..........................................................................................................36 SDIO Host Block Diagram ................................................................................................................39 "No Response" and "No Data" Operation .........................................................................................40 Multiple Block Read Operation .........................................................................................................40 Multiple Block Write with Card Busy Operation ................................................................................40 Read Wait Controlled by Stopping Clock..........................................................................................41 Command Token Format ..................................................................................................................41 Response Token Format .................................................................................................................42 Data Packet Format, Standard Bus (Only DAT0 Used)....................................................................42 Data Packet Format, Wide Bus (All Four Data Lines Used) .............................................................42 Host Initialization Flow Chart ............................................................................................................44 CCIC Block Diagram ........................................................................................................................46 Internal Structure of Serial EEPROM ...............................................................................................50 Functional Overview........................................................................................................................................30
3
3.1 3.2 3.3 3.4 3.5 3.6
Register Description........................................................................................................................ 55
Registers Introduction .....................................................................................................................................55 Figure 20: Register Conventions ......................................................................................................................55 PCI Configuration Register File.......................................................................................................................56 Global Control Registers .................................................................................................................................81 NAND Flash Unit .............................................................................................................................................90 SDIO Host Controller Registers ....................................................................................................................101 CMOS Camera Interface Controller ..............................................................................................................124
4
Mechanical Drawings .................................................................................................................... 140
Figure 21: 128-pin TQFP Mechanical Drawing ................................................................................................140
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Copyright (c) 2007 Marvell July 17, 2007, Preliminary
List of Figures
5
5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8
Electrical Specifications ............................................................................................................... 141
Absolute Maximum Ratings ..........................................................................................................................141 Recommended Operating Conditions ...........................................................................................................141 Package Thermal Conditions ........................................................................................................................142 DC Electrical Characteristics.........................................................................................................................142 Input Clock Specifications .............................................................................................................................143 Internal Resistors ..........................................................................................................................................144 PCI Bus Interface Unit...................................................................................................................................144 NAND Flash Controller..................................................................................................................................146 Figure 22: Figure 23: Figure 24: Figure 25: NAND Flash Command Write .........................................................................................................147 NAND Flash Address Write ............................................................................................................147 NAND Flash Data Write ..................................................................................................................148 NAND Flash Data Read..................................................................................................................148 SDIO Low Speed Timing Diagram..................................................................................................150 SDIO High Speed Timing Diagram .................................................................................................151 CMOS Camera Interface TWSI Timing Diagram ............................................................................152 CMOS Camera Interface Timing Diagram ......................................................................................152 JTAG Timing Diagram ....................................................................................................................154
5.9
SDIO .............................................................................................................................................................149 Figure 26: Figure 27:
5.10
CMOS Camera Interface...............................................................................................................................152 Figure 28: Figure 29:
5.11 5.12
JTAG Test Interface ......................................................................................................................................153 Figure 30: GPIO .............................................................................................................................................................155
6
6.1 6.2
Part Order Numbering/Package Marking..................................................................................... 156
Part Order Numbering ...................................................................................................................................156 Figure 31: Figure 32: Sample Part Number .....................................................................................................................156 Commercial Package Marking and Pin 1 Location .........................................................................157 Package Marking ..........................................................................................................................................157
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88ALP01 Datasheet
List of Registers
1
1.1 1.2 1.3
Signal Description ........................................................................................................... 21
Signal Diagram................................................................................................................................................21 128-Pin TQFP Package ..................................................................................................................................22 Pin Description ................................................................................................................................................23
2
2.1 2.2
Functional Description.................................................................................................... 29
System Overview ............................................................................................................................................29 Functional Overview........................................................................................................................................30
3
3.1 3.2
Register Description ....................................................................................................... 55
Registers Introduction .....................................................................................................................................55 PCI Configuration Register File.......................................................................................................................56
Table 27:
Offset:
Vendor ID Register .................................................................................................................................... 60
0x00
Table 28:
Offset:
Device ID Register..................................................................................................................................... 60
0x02
Table 29:
Offset:
Command Register.................................................................................................................................... 60
0x04
Table 30:
Offset:
Status Register .......................................................................................................................................... 62
0x06
Table 31:
Offset:
Revision ID Register.................................................................................................................................. 63
0x08
Table 32:
Offset:
Programming Interface Register, Lower Byte............................................................................................ 63
0x09
Table 33:
Offset:
Sub-Class Register, Middle Byte............................................................................................................... 63
0x0A
Table 34:
Offset:
Base-Class Register, Upper Byte.............................................................................................................. 63
0x0B
Table 35:
Offset:
Cache Line Size Register .......................................................................................................................... 64
0x0C
Table 36:
Offset:
Latency Timer Register ............................................................................................................................. 64
0x0D
Table 37:
Offset:
Base-Class Register.................................................................................................................................. 65
0x0E
Table 38:
Offset:
Built-in Self Test Register .......................................................................................................................... 65
0x0F
Table 39:
Offset:
Base Address Register (1st)...................................................................................................................... 65
0x10
Table 40:
Offset:
Subsystem Vendor ID Register ................................................................................................................. 66
0x2C
Table 41:
Offset:
Subsystem ID Register.............................................................................................................................. 66
0x2E
Table 42:
Offset:
New Capabilities Pointer Register ............................................................................................................. 67
0x34
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Copyright (c) 2007 Marvell July 17, 2007, Preliminary
List of Registers
Table 43:
Offset:
Interrupt Line Register ............................................................................................................................... 67
0x3C
Table 44:
Offset:
Interrupt Pin Register................................................................................................................................. 67
0x3D
Table 45:
Offset:
Min_Gnt Register....................................................................................................................................... 68
0x3E
Table 46:
Offset:
Max_Lat Register ...................................................................................................................................... 68
0x3F
Table 47:
Offset:
SD Slot Information Register ..................................................................................................................... 69
0x40
Table 48:
Offset:
Access Control Register ............................................................................................................................ 69
0x80
Table 49:
Offset:
VPD Control Register ................................................................................................................................ 70
0x84
Table 50:
Offset:
Power Management Capability ID Register............................................................................................... 71
0x88
Table 51:
Offset:
Power Management Next Item Pointer...................................................................................................... 71
0x89
Table 52:
Offset:
Power Management Capabilities Register ................................................................................................ 72
0x8A
Table 53:
Offset:
Power Management Control/Status Register ............................................................................................ 73
0x8C
Table 54:
Offset:
Power Management Data Register ........................................................................................................... 74
0x8F
Table 56:
Offset:
VPD Capability ID Register ....................................................................................................................... 75
0x90
Table 57:
Offset:
VPD Next Item Pointer .............................................................................................................................. 75
0x91
Table 58:
Offset:
VPD Address Register............................................................................................................................... 75
0x92
Table 59:
Offset:
VPD Data Registers .................................................................................................................................. 76
0x94
Table 60:
Offset:
VPD Serial EEPROM Loader Control Register ......................................................................................... 76
0x9A
Table 61:
Offset:
MSI Capability ID Register (MSI Cap ID) .................................................................................................. 76
0x9C
Table 62:
Offset:
MSI Next Item Pointer Register ................................................................................................................. 77
0x9D
Table 63:
Offset:
MSI Message Control Register.................................................................................................................. 77
0x9E
Table 64:
Offset:
MSI Message Lower Address Register ..................................................................................................... 78
0xA0
Table 65:
Offset:
MSI Message Upper Address Register ..................................................................................................... 78
0xA4
Table 66:
Offset:
MSI Message Data Register...................................................................................................................... 79
0xA8
Table 67:
Offset:
Calibration Control Register ...................................................................................................................... 79
0xB4
Table 68:
Offset:
Calibration Status Register........................................................................................................................ 80
0xB6
Table 69:
Offset:
Discard Counter Register .......................................................................................................................... 80
0xB8
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Doc. No. MV-S103921-00 Rev. - Page 15
88ALP01 Datasheet
Table 70:
Offset:
Retry Counter Register.............................................................................................................................. 80
0xBA
3.3
Global Control Registers .................................................................................................................................81
Table 72:
Offset:
Control/Status Register ............................................................................................................................. 81
0x3004
Table 73:
Offset:
Interrupt Source Register .......................................................................................................................... 83
0x3008
Table 74:
Offset:
Interrupt Mask Register ............................................................................................................................. 83
0x300C
Table 75:
Offset:
Interrupt HW Error Source Register .......................................................................................................... 84
0x3010
Table 76:
Offset:
Interrupt HW Error Mask Register ............................................................................................................. 85
0x3014
Table 77:
Offset:
PLL Control Register ................................................................................................................................. 85
0x3030
Table 78:
Offset:
Block Control Register............................................................................................................................... 86
0x3034
Table 79:
Offset:
GPIO Functional Control Register ............................................................................................................. 86
0x3038
Table 80:
Offset:
Test Control Register................................................................................................................................. 87
0x3158
Table 81:
Offset:
General Purpose I/O Register ................................................................................................................... 87
0x315C
Table 82:
Offset:
VPD TWSI (HW) Control Register............................................................................................................. 88
0x3160
Table 83:
Offset:
VPD TWSI (HW) Data Register................................................................................................................. 89
0x3164
Table 84:
Offset:
VPD TWSI (HW) IRQ Register .................................................................................................................. 89
0x3168
Table 85:
Offset:
VPD TWSI (SW) Register.......................................................................................................................... 90
0x316C
3.4
NAND Flash Unit .............................................................................................................................................90
Table 87:
Offset:
Control Register......................................................................................................................................... 91
0x00
Table 88:
Offset:
Control Register 2...................................................................................................................................... 92
0x04
Table 89:
Offset:
Control Register 3...................................................................................................................................... 93
0x08
Table 90:
Offset:
Status Register .......................................................................................................................................... 93
0x0C
Table 91:
Offset:
Interrupt Register....................................................................................................................................... 93
0x10
Table 92:
Offset:
Interrupt Mask Register ............................................................................................................................. 94
0x14
Table 93:
Offset:
Data Length Register................................................................................................................................. 94
0x18
Table 94:
Offset:
Address Register ....................................................................................................................................... 94
0x1C
Table 95:
Offset:
Address Register 2 .................................................................................................................................... 95
0x20
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List of Registers
Table 96:
Offset:
Timing Parameter Register 1..................................................................................................................... 95
0x24
Table 97:
Offset:
Timing Parameter Register 2..................................................................................................................... 96
0x28
Table 98:
Offset:
Timing Parameter Register 3..................................................................................................................... 96
0x2C
Table 99:
Offset: Offset: Offset: Offset: Offset: Offset: Offset: Offset: Offset: Offset: Offset: Offset: Offset: Offset: Offset:
Non-Memory Read Data Register ............................................................................................................. 97
0x30 0x34 0x38 0x3C 0x40 0x44 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x1000 to 0x183C 0x2000 to 0x283C
Table 100: Read ECC Generated Code Register ....................................................................................................... 97 Table 101: Read ECC Read Code Register................................................................................................................ 97 Table 102: Read ECC Result Register........................................................................................................................ 97 Table 103: DMA Control Register................................................................................................................................ 98 Table 104: DMA Address Register 0 ........................................................................................................................... 98 Table 105: RS ECC Decode CRC Register ................................................................................................................ 98 Table 106: RS ECC Decode Syndrome 0 and 1 Register........................................................................................... 99 Table 107: RS ECC Decode Syndrome 2 and 3 Register........................................................................................... 99 Table 108: RS ECC Decode Syndrome 4 and 5 Register........................................................................................... 99 Table 109: RS ECC Decode Syndrome 6 and 7 Register......................................................................................... 100 Table 110: Control Register 4.................................................................................................................................... 100 Table 111: NAND I/O Drive Strength Register .......................................................................................................... 100 Table 112: Read Data Registers ............................................................................................................................... 100 Table 113: Write Data Registers ............................................................................................................................... 101
3.5
SDIO Host Controller Registers ....................................................................................................................101
Table 115: System Address Low Register ................................................................................................................ 103
Offset: Offset: Offset: Offset: Offset: Offset: Offset: 0x00 0x02 0x04 0x06 0x08 0x0A 0x0C
Table 116: System Address High Register................................................................................................................ 103 Table 117: Block Size Register ................................................................................................................................. 103 Table 118: Block Count Register............................................................................................................................... 104 Table 119: Argument Low Register ........................................................................................................................... 104 Table 120: Argument High Register .......................................................................................................................... 104 Table 121: Transfer Mode Register........................................................................................................................... 104
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Doc. No. MV-S103921-00 Rev. - Page 17
88ALP01 Datasheet
Table 122: Command Register.................................................................................................................................. 105
Offset: Offset: Offset: Offset: Offset: Offset: Offset: Offset: Offset: Offset: Offset: Offset: Offset: Offset: Offset: Offset: Offset: Offset: Offset: Offset: Offset: Offset: Offset: Offset: Offset: Offset: 0x0E 0x10 0x12 0x14 0x16 0x18 0x1A 0x1C 0x1E 0x20 0x22 0x24 0x26 0x28 0x2A 0x2C 0x2E 0x30 0x32 0x34 0x36 0x38 0x3A 0x3C 0x40 0x42
Table 123: Response Register 0 ............................................................................................................................... 106 Table 124: Response Register 1 ............................................................................................................................... 106 Table 125: Response Register 2 ............................................................................................................................... 106 Table 126: Response Register 3 ............................................................................................................................... 106 Table 127: Response Register 4 ............................................................................................................................... 107 Table 128: Response Register 5 ............................................................................................................................... 107 Table 129: Response Register 6 ............................................................................................................................... 107 Table 130: Response Register 7 ............................................................................................................................... 107 Table 131: Buffer Data Port0 Register ...................................................................................................................... 107 Table 132: Buffer Data Port1 Register ...................................................................................................................... 108 Table 133: Present State Register 0 ......................................................................................................................... 108 Table 134: Present State Register 1 ......................................................................................................................... 109 Table 135: Host Control Register .............................................................................................................................. 110 Table 136: Block Gap Control Register ..................................................................................................................... 111 Table 137: Clock Control Register............................................................................................................................. 112 Table 138: Timeout Control/Software Reset Register ............................................................................................... 113 Table 139: Normal Interrupt Status Register ............................................................................................................. 114 Table 140: Error Interrupt Status Register................................................................................................................. 115 Table 141: Normal Interrupt Status Enable Register................................................................................................. 116 Table 142: Error Interrupt Status Enable Register .................................................................................................... 117 Table 143: Normal Interrupt Status Interrupt Enable Register .................................................................................. 118 Table 144: Error Interrupt Status Interrupt Enable Register ...................................................................................... 119 Table 145: Auto CMD12 Error Status Register ......................................................................................................... 120 Table 146: Capabilities Register................................................................................................................................ 120 Table 147: Capabilities Register 1............................................................................................................................. 121
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List of Registers
Table 148: Capabilities Register 2............................................................................................................................. 121
Offset: Offset: Offset: Offset: Offset: Offset: Offset: Offset: Offset: Offset: Offset: 0x44 0x46 0x48 0x4A 0x4C 0x4E 0x60 0x6A 0x7C 0xFC 0xFE
Table 149: Capabilities Register 3............................................................................................................................. 121 Table 150: Maximum Current Register 0................................................................................................................... 122 Table 151: Maximum Current Register 1................................................................................................................... 122 Table 152: Maximum Current Register 2................................................................................................................... 122 Table 153: Maximum Current Register 3................................................................................................................... 122 Table 154: I/O Control Register................................................................................................................................. 123 Table 155: Command 1 Register............................................................................................................................... 123 Table 156: SD Drive Strength Register ..................................................................................................................... 123 Table 157: Slot Interrupt Status Register .................................................................................................................. 123 Table 158: Host Control Version Register ................................................................................................................. 124
3.6
CMOS Camera Interface Controller ..............................................................................................................124
Table 160: Y0-Base Address Register ...................................................................................................................... 125
Offset: Offset: Offset: Offset: Offset: Offset: Offset: Offset: Offset: Offset: Offset: Offset: Offset: Offset: 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34
Table 161: Y1-Base Address Register ...................................................................................................................... 125 Table 162: Y2-Base Address Register ...................................................................................................................... 125 Table 163: U0-Base Address Register ...................................................................................................................... 126 Table 164: U1-Base Address Register ...................................................................................................................... 126 Table 165: U2-Base Address Register ...................................................................................................................... 126 Table 166: V0-Base Address Register ...................................................................................................................... 126 Table 167: V1-Base Address Register ...................................................................................................................... 127 Table 168: V2-Base Address Register ...................................................................................................................... 127 Table 169: Image Pitch Register ............................................................................................................................... 127 Table 170: IRQ RAW Status Register ....................................................................................................................... 127 Table 171: IRQ Mask Register .................................................................................................................................. 128 Table 172: IRQ Status Register................................................................................................................................. 129 Table 173: Image Size Register ................................................................................................................................ 131
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88ALP01 Datasheet
Table 174: Image Offset Register.............................................................................................................................. 131
Offset: Offset: Offset: Offset: Offset: Offset: Offset: Offset: Offset: 0x38 0x3C 0x40 0x88 0x8C 0x90 0xB4 0xB8 0xBC
Table 175: Control 0 Register.................................................................................................................................... 132 Table 176: Control 1 Register.................................................................................................................................... 135 Table 177: Clock Control Register............................................................................................................................. 136 Table 178: SRAM TC0 Register (Test Only) ............................................................................................................. 137 Table 179: SRAM TC1 Register (Test Only) ............................................................................................................. 137 Table 180: General Purpose (GPR) Register............................................................................................................ 137 Table 181: TWSI Control 0 Register.......................................................................................................................... 138 Table 182: TWSI Control 1 Register.......................................................................................................................... 139
4 5
5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 5.10 5.11 5.12
Mechanical Drawings .................................................................................................... 140 Electrical Specifications ............................................................................................... 141
Absolute Maximum Ratings ..........................................................................................................................141 Recommended Operating Conditions ...........................................................................................................141 Package Thermal Conditions ........................................................................................................................142 DC Electrical Characteristics.........................................................................................................................142 Input Clock Specifications .............................................................................................................................143 Internal Resistors ..........................................................................................................................................144 PCI Bus Interface Unit...................................................................................................................................144 NAND Flash Controller..................................................................................................................................146 SDIO .............................................................................................................................................................149 CMOS Camera Interface...............................................................................................................................152 JTAG Test Interface ......................................................................................................................................153 GPIO .............................................................................................................................................................155
6
6.1 6.2
Part Order Numbering/Package Marking..................................................................... 156
Part Order Numbering ...................................................................................................................................156 Package Marking ..........................................................................................................................................157
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Copyright (c) 2007 Marvell July 17, 2007, Preliminary
Signal Description
Signal Diagram
1
1.1
Signal Description
Signal Diagram
Figure 1: Signal Diagram
NF_ALE NF_CE[1]n NF_CE[0]n NF_REn NF_WEn NF_CLE NF_WPn NF_RDY NF_IO[7:0]
SD_CLK SD/SDIO Interface NAND Flash CLK RSTn
M66EN INTAn PMEn AD[31:0] PAR FRAMEn TRDYn
SD_CMD SD_DATA[3:0]
HSYNC VSYNC PIXDATA[7:0] PIXCLK TWSI_SCLK SENSOR_CTL0 SENSOR_CTL1 PIXMCLK TWSI_SDATA
PCI Interface Camera Interface
IRDYn STOPn DEVSELn IDSEL CLK_RUNn PERRn SERRn GNTn REQn CBEn[3:0]
88ALP01
VPD_CLK VPD_DATA
TWSI (Serial EEPROM) Main Clock Interface (PLL)
REF_CLK
TESTMODE TDI TCK TMS TDO ZP_REF ZN_REF
12CNTL
Core VDD Control JTAG and Test Interface GPIO Interface
RSET
GPIO[3:0]
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Doc. No. MV-S103921-00 Rev. - Page 21
88ALP01 Datasheet
1.2
128-Pin TQFP Package
AVSS_PLL REF_CLK AVDD_PLL RSTn AD[29] AD[27] GNTn AD[30] REQn AD[26] VDDO CLK VDDO VDD VDDO PMEn INTAn AD[28] AD[31] CBEn[ 3] AD[24] AD[25] AD[23] IDSEL AD[22] AD[20] AD[18] AD[21] AD[19] AD[17] AD[16] CBEn[ 2] 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
Figure 2: TQFP Pinout
Doc. No. MV-S103921-00 Rev. - Page 22 Document Classification: Proprietary Information
HSYNC TWSI_SDATA TWSI_SCLK NF_IO[7] NF_IO[6] NF_IO[5] NF_IO[4] NF_IO[3] NF_IO[2] NF_IO[1] VDDO VDDO VDD NF_IO[0] NF_WPn NF_CE[1]n NF_WEn NF_ALE NF_CLE NF_CE[0]n NF_REn NF_RDY SD_DATA[2] SD_DATA[3] SD_CMD SD_CLK SD_DATA[0] SD_DATA[1] PERRn SERRn VDDO VDDO
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
TMS TDI TESTMODE TDO TCK VDDO VDDO VDD VPD _DATA VPD_CLK GPIO[ 0] GPIO[ 1] GPIO[ 2] 12CNTL RSET GPIO[ 3] PIXMCLK PIXDATA[ 7] PIXDATA[ 6] PIXDATA[ 5] PIXDATA[ 4] PIXDATA[ 3] PIXDATA[ 2] VDDOC VDDOC VDD PIXDATA[ 1] PIXDATA[ 0] SENSOR_CTL0 SENSOR_CTL1 PIXCLK VSYNC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
EPAD - VSS
88ALP01
Top View
FRAMEn IRDYn PAR VDD VDDO CLK_RUNn TRDYn DEVSELn STOPn CBEn[1] AD[15] AD[12] ZN_REF ZP_REF AD[14] AD[13] AD[10] AD[11] AD[9] VDD VDDO AD[8] AD[7] CBEn[0] AD[4] AD[5] AD[6] AD[3] AD[1] AD[0] AD[2] M66EN
Copyright (c) 2007 Marvell July 17, 2007, Preliminary
Signal Description
Pin Description
1.3
Pin Description
Table 1:
P in Typ e A D H I I/O mA n O PD PU Z
Pin Type Definitions
Defi ni ti o n Analog Open drain output Input with hysteresis Input Input/output DC sink capability Active low Output Weak internal pull down Weak internal pull up Tri-state output
For resistor strengths, refer to Section 5.6, Internal Resistors, on page 144. Note
Table 2:
Package P in # 58 57 56, 55, 60, 59
SD/SDIO Interface (3.3V)
Pin Name SD_CLK SD_CMD SD_DATA[3:0] Pi n Typ e O I/O I/O D e s c r ip t i o n SD/SDIO Clock Output SD/SDIO Command/Response SD/SDIO Data Line [3:0]
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Doc. No. MV-S103921-00 Rev. - Page 23
88ALP01 Datasheet
Table 3:
Package P in #
PCI Interface (3.3V)
Pin Name Pi n Typ e I/O D e s c r ip t i o n Multiplexed Data and Address Lines
AD[31:0] 110, 121, 124, 111, 123, 119, 107, 108, 106, 104, 101, 103, 100, 102, 99, 98, 86, 82, 81, 85, 79, 80, 78, 75, 74, 70, 71, 72, 69, 66, 68, 67 109, 97, 87, 73 117 91 CBEn[3:0] CLK CLK_RUNn
I/O, Z I I/O
Bus Command and Byte Enable Lines, active low PCI Bus Clock Frequency from 0 to 66 MHz. Clock Run, active low The CLK_RUNn pin is a mobile device clock management signal. CLK_RUNn is an active low pin that follows the guidelines described in the PCI Mobile Design Guide.
89
DEVSELn
I/O, Sustained Z Device Select, active low Asserted by the adapter with medium DEVSELn timing. I/O, Sustained Z Cycle Frame, active low I, Z I O, D Bus Grant, active low Initialization Device Select Interrupt Signal, active low Indicates an Interrupt request from the adapter to the system. The assertion and deassertion of the INTAn is asynchronous to CLK. A pending request is cleared by the interrupt service of the device driver. External 4.7 k pull up
96 122 105 112
FRAMEn GNTn IDSEL INTAn
95 65
IRDYn M66EN
I/O, Sustained Z Initiator Ready, active low I 66 MHz Enable Indicates to a device whether the bus segment is operating at 66 or 33 MHz. Even Parity over AD[31:0] and CBEn[3:0]
94 61
PAR PERRn
I/O, Z
I/O, Sustained Z Parity Error, active low Asserted by the adapter for all data parity errors detected, if enabled. O, D Power Management Event, active low
113
PMEn
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Signal Description
Pin Description
Table 3:
Package P in # 120
PCI Interface (3.3V) (Continued)
Pin Name REQn Pi n Typ e O, Z D e s c r ip t i o n Bus Request, active low Asserted by the adapter to gain bus ownership, kept asserted until second last data phase of a transaction. Reset Signal, active low System Error Signal, active low Asserted by adapter for all address parity errors detected, if enabled.
125 62
RSTn SERRn
I O, D
88
STOPn
I/O, Sustained Z Target Stop Request, active low Used by the adapter only for target disconnect with/without data. I/O, Sustained Z Target Ready, active low
90
TRDYn
Table 4:
Package P in # 50
NAND Flash (3.3V)
Pin Name NF_ALE Pi n Typ e O, PU D e s c r ip t i o n NAND Flash Address Enable When this signal is high, writes to NAND Flash indicates address configuration write. NAND Flash Chip Enable 2, active low When this signal is high, the NAND Flash is enabled for access. NAND Flash Chip Enable, active low When this signal is high, the NAND Flash is enabled for access. NAND Flash Command Latch Enable NAND Flash Data I/O [7:0] When NF_IO[0] is strapped low during power-on reset, serial EEPROM load is enabled. When NF_IO[1] is strapped low during power-on reset, the internal PLL is bypassed. NF_RDY I, PU NAND Flash Ready This input signal indicates status of Flash operations to the controller. External 4.7 k pull up NAND Flash Read Enable, active low NAND Flash Write Enable, active low NAND Flash Write Protect, active low Protects against inadvertent program and erase options. All program and erase operations are disabled when this signal is asserted low.
48
NF_CE[1]n
O, PU
52
NF_CE[0]n
O, PU
51 36, 37, 38, 39, 40, 41, 42, 46
NF_CLE NF_IO[7:0]
O, PU I/O, PU
54
53 49 47
NF_REn NF_WEn NF_WPn
O, PU O, PU O, PU
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Doc. No. MV-S103921-00 Rev. - Page 25
88ALP01 Datasheet
Table 5:
Package P in # 33 31 18, 19, 20, 21, 22, 23, 27, 28 17 29
Camera Interface (2.5 or 3.3V)
Pin Name HSYNC PIXCLK PIXDATA[7:0] Pi n Typ e I/O I I D e s c r ip t i o n Horizontal Sync driven by external CMOS sensor Pixel Clock Pixel Data [7:0] Synchronous to PIXCLK. PIXDATA[7:6], PD (Default) Pixel Master Clock Sensor Control 0 This output signal is used to control the external CMOS sensor's reset or power down pin. It requires an external pull-up or pull-down to put the external CMOS sensor into reset/power-down mode after boot. Sensor Control 1 This output signal is used to control the external CMOS sensor's reset or power down pin. It requires an external pull-up or pull-down to put the external CMOS sensor into reset/power-down mode after boot. TWSI Serial Clock An external pull-up resistor is needed, for example, 2k. TWSI Serial Data An external pull-up resistor is needed, for example, 2k. Vertical Sync driven by external CMOS sensor
PIXMCLK SENSOR_CTL0
O O
30
SENSOR_CTL1
O
35
TWSI_SCLK
O
34
TWSI_SDATA
I/O
32
VSYNC
I/O
Table 6:
Package P in # 10
VPD TWSI (Serial EEPROM, 3.3V)
Pin Name VPD_CLK Pi n Typ e O D e s c r ip t i o n TWSI Bus Clock Line to Serial EEPROM External 4.7 k pull up When VPD_CLK is strapped high during power-on reset, it signals the capability to operate in 66 MHz.
9
VPD_DATA
I/O
TWSI Bus Data Line to Serial EEPROM External 4.7 k pull up
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Signal Description
Pin Description
Table 7:
Package P in # 127
Main Clock Interface (PLL, 3.3V)
Pin Name REF_CLK Pi n Typ e I D e s c r ip t i o n Input from 24 MHz Reference Clock (external oscillator)
Table 8:
Package P in # 16, 13, 12, 11
GPIO Interface (3.3V)
Pin Name GPIO[3:0] Pi n Typ e I/O D e s c r ip t i o n General Purpose I/O The GPIO pins have the following functions: GPIO[3]: Camera power enable GPIO[2]: SD socket power enable GPIO[1]: SD card write protection, active low. A 100 k pull up is required. GPIO[0]: SD card active, active low (for LED)
Table 9:
Package P in # 5
Joint Test Action Group (JTAG) and Test Interface (3.3V)
Pin Name TCK Pi n Typ e I D e s c r ip t i o n Test Clock Used to clock state information and test data into and out of the device during operation of the TAP. Pull down for normal operation Test Data In for JTAG Boundary Scan Test Path Used to serially shift test data and instructions into the device during TAP operation. Pull down for normal operation Test Data Out for JTAG Boundary Scan Test Path, active low Used to shift test data and test instructions serially out of the device during TAP operation. SD card detect for normal operation A 100 k pull up to 3.3V is required.
2
TDI
I
4
TDO
I/O
3 1
TESTMODE TMS
I I
Selection of Internal Test 4.7 k pull down for normal operation Test Mode Select Used to control the state of the TAP controller in the device. Pull down Calibration Pad, Reference for PCIZN 27.1 1% pull up
84
ZN_REF
I/O
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Doc. No. MV-S103921-00 Rev. - Page 27
88ALP01 Datasheet
Table 9:
Package P in # 83
Joint Test Action Group (JTAG) and Test Interface (3.3V) (Continued)
Pin Name ZP_REF Pi n Typ e I/O D e s c r ip t i o n Calibration Pad, Reference for PCIZP 33.4 1% pull down
Table 10: Core VDD Control (1.2V)
Package P in # 14 Pin Name 12CNTL Pi n Typ e O D e s c r ip t i o n Regulator Control This signal controls an external PNP transistor to generate the 1.2V power supply. RSET 6 k 1% resistor pull down
15
RSET
A
Table 11: Power and Ground
Package P in # 126 128 Pin Name AVDD_PLL AVSS_PLL Pi n Typ e A, Power A, Ground Power Power D e s c r ip t i o n Analog 3.3V Power Supply Analog Ground 1.2V (5%) Power Supply 3.3V (5%) Power Supply
8, 26, 45, 77, VDD 93, 115 6, 7, 43, 44, VDDO 63, 64, 76, 92, 114, 116, 118 24, 25 VDDOC
Power
2.5V to 3.3V (5%) Power Supply I/O supply for camera interface Needed to match camera I/O level but always on
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Functional Description
System Overview
2
2.1
Functional Description
System Overview
The 88ALP01 is a single-chip, triple function device for PCI Local Bus system and is designed to address high-performance, low power system requirements. The 88ALP01 integrates a NAND Flash controller, an SD/SDIO host controller, and a CMOS Camera Interface Controller. Figure 3 shows the main components of a PCI sub-system using the 88ALP01. Each component is described in the following sections.
Figure 3: 88ALP01 System Diagram
3.3V 2.5V 1.2V 1.2V CTL
SD/SDIO Connector
External Power Transistor PCI Bus 32 bits at 33/66 MHz 88ALP01
TWSI Pixel Interface Camera Module Connector
TWSI EEPROM (VPD)
24/48 MHz Oscillator
8-bit NAND Flash Device
2.1.1
2.1.1.1
System Component Description
Power Supplies
The 88ALP01 requires 3.3V, 2.5V, and 1.2V external supplies. The 2.5V supply is required for 2.5V camera interface. If the camera interface supports 3.3V, then the 2.5V supply can be eliminated. The 88ALP01 also has an internal voltage regulator that provides a 1.2V control output to be used with an external transistor to provide the 1.2V supply for the on-chip digital logics. If the system has 1.2V supply, the internal regulator output should be left floating.
Copyright (c) 2007 Marvell July 17, 2007, Preliminary Document Classification: Proprietary Information
Doc. No. MV-S103921-00 Rev. - Page 29
88ALP01 Datasheet
2.1.1.2
External Reference Clock
The 88ALP01 requires a 24 MHz external reference clock (from an external oscillator). The 88ALP01 has an internal programmable PLL that provides the core clock for different on-chip modules. The 88ALP01 generates a 96 MHz clock for NAND Flash and a 48 MHz clock for SD and the camera interface. The 88ALP01 can also be configured to bypass the internal PLL and use a 48 MHz clock input. In this case, the 48 MHz clock is connected to all modules.
2.1.1.3
External TWSI EEPROM (VPD)
The 88ALP01 can optionally use an external serial EEPROM (1 or 2 KB). After PCI reset, the 88ALP01 will automatically overwrite PCI Configuration Registers (and other registers) with data from the EEPROM. This is how a system manufacturer alters the default PCI information.
2.2
Functional Overview
Figure 4 shows the main blocks of the 88ALP01. Each interface and block is described in the following sections. The functions are as follows: Function 0--NAND Flash Controller Function 1--SD/SDIO Controller Function 2--CMOS Camera Interface Controller
Figure 4: 88ALP01 Functional Block Diagram
Bus Master Arbiter
Master
DMA SM
Reed-Solomon ECC
PCI Interface Slave NAND Register Set NAND Access SM
Bus Slave Decode
Clock Reset
NAND Clock Reset
Write Buffer
Read Buffer
NAND Flash Controller SD/SDIO Controller Camera Interface Controller
Configuration Register Sets
Interrupt Wakeup (INTAn, PMEn)
Serial EEPROM Interface
PLL
JTAG
2.2.1
PCI Bus Interface Unit
The PCI Bus Interface Unit (BIU) provides the framework for interfacing with the PCI Local Bus. It comprises several state machines running synchronously with the PCI bus clock signal (CLK). Except for the interrupt signal that is independent from the PCI bus clock, all outputs are synchronously generated with the rising edge of CLK. All inputs are synchronously sampled. The BIU handles:
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Copyright (c) 2007 Marvell July 17, 2007, Preliminary
Functional Description
Functional Overview
Access to the configuration data Access to memory mapped resources PCI bus master operation of 88ALP01 Data transfers via the PCI bus are 4 bytes wide (32 bit). The transfer rate also depends on the bus clock (0 to 33 MHz / up to 66 MHz). The BIU handles the basic protocol for accesses via the PCI bus. It is built of several state machines running synchronously with the PCI bus CLK signal. All inputs are synchronously sampled. All outputs are synchronously generated on the rising edge of CLK to assure that interrupts are serviced independently of the PCI clock speed. The 88ALP01 is a 32-bit device. It is mapped into the lower 4 GB of the address space and therefore ignores all dual address cycles. The master section of the BIU is treated in more detail when data transfer over the PCI bus is discussed. It is not of interest in connection with the programming interface since bus master operations are performed by the 88ALP01 hardware according to the preconfigured control registers.
2.2.1.1
Slave Access to Configuration Space
Slave access to the configuration space is also not of primary interest for the programming interface. However, it may be valuable for troubleshooting with PCI bus analyzers and exerciser tools. This bus operation is performed by the target sequencer state machine. Acceptance and termination of a transaction is determined by a backend consisting of the configuration decoder and the Configuration Register File. The adapter responds to type 0 configuration accesses (AD[1:0] = "00", IDSELn). If the configuration space is targeted for a burst operation, it responds with a disconnect on the first data transfer. The Configuration Register File can be accessed with 8-bit, 16-bit, or 32-bit transfers. Configuration transactions are not aborted (target initiated termination). On read transactions, all data is driven as defined for full 32-bit accesses independent of CBEn[3:0].
2.2.1.2
Slave Access to Memory Resources
There is only one accessible resource, the Memory Mapped I/O-Resources. Accesses to memory mapped I/O-Resources are performed by the target sequencer state machine. Acceptance and termination of a transaction is determined by a backend consisting of the control decoder and the control register file. The control registers have to be accessed with the minimum data width (8-, 16-, or 32-bit) transfers depending on the definition of the registers. On read transactions, all data is driven as defined for full 32-bit accesses independently of CBEn[3:0]. If the memory resources are targeted for a burst operation, the BIU responds with a disconnect on the first data transfer. All PCI memory cycles are preset to simple memory read and memory write cycles.
2.2.1.3
Master Access
The master sequencer state machine is controlled by giving address, guaranteed number of bytes to be transferred (plus minor additional informations) on a per-cycle basis from one of the three master backends (queues). If not owner of the PCI bus already, bus is requested. The BIU releases ownership of the bus for several reasons: Number of bytes to transfer is zero
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Cache line size boundary is reached and the remaining number of bytes to be transferred is below cache line size Latency counter has expired Servicing one of the backends is reported to the bus arbiter. The number of transferred bytes is reported to the backend on a per cycle base. The default transfer is burst transfer unless disabled by Disable Burst. Supported commands are: Memory Write Memory Write And Invalidate Memory Read Memory Read Line Memory Read Multiple Memory Write And Invalidate is used instead of Memory Write, if the guaranteed number of bytes to be transferred is higher than the cache line size. Memory Read Line is used instead of Memory Read, if the guaranteed number of bytes to be transferred is higher than eight. If the guaranteed number of bytes to be transferred is higher than one cache line size at least, Memory Read Multiple is used instead of Memory Read Line. The commands Memory Write And Invalidate, Memory Read Line, and Memory Read Multiple may be disabled individually by setting the appropriate bits in Access Control (Configuration Register File). If a cycle is terminated by Target or Master Abort, this fact is reported to RTABORT or RMABORT (Status Register), interrupt IRQ Master and IRQ Status are set and the master sequencer state machine is locked. This situation must be solved by resetting the state machine using a master reset. A target retry is serviced by retrying the terminated cycle.
2.2.1.4
Parity Generation/Check
Parity is generated and checked on transmit and receive data paths with respect to the system logic. This condition applies both to the PCI Interface and to the internal RAM interface. Parity on the PCI bus is generated, checked, and reported according to the PCI specification. PCI parity generation and checking follows the PCI specification for even parity on 32-bit words. All other parity generation and checking performs even parity on bytes.
Parity Checking/Generating on PCI as Target
Read data parity is generated for read accesses to adapter resources in the system logic. Write data parity is checked for write accesses to adapter resources in the system logic. Address parity is checked for all address phases running on the bus. If a write data parity error is detected, Parity Error is set. Bus signal PERRn is asserted, if Parity Report Response Enable is set. If an address parity error is detected, Parity Error is set. Bus signal SERRn is asserted and Signaled Error is set, if SERRn Enable and Parity Report Response Enable are set.
Parity Checking/Generating on PCI as Master
Write data parity is generated for all write accesses to the system memory. Read data parity is checked for all read accesses from the system memory. Address parity is generated for all address phases generated on the bus. If a read data parity error is detected, Parity Error is set. Data Parity Error detected is set, if Parity Report Response Enable is set. If on a write access, PERRn is sampled as asserted, Parity Error is set. Data Parity Error detected is set, if enabled by Parity Report Response Enable. If Data Parity Error Detected is set, interrupt field in the Interrupt HW Error Source Register (Table 75 p. 84) is set. If Parity Error is set, interrupt IRQ Status is set (see also Status Register (Table 30 p. 62)).
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Functional Description
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2.2.2
NAND Flash Controller
The NAND Flash Controller (NFC) provides interfaces to regular NAND Flash-based storage (for example, Samsung K9F5616Q0C, Toshiba TC58DVM82A1FT100, and more). It supports: Configurability to interface with different 8-bit NAND Flash devices Either 512 byte or 2 KB page sizes Configurability to work with different single-chip NAND Flash sizes from 128 Mb to 64 Gb Basic NAND Flash functions, including page program/read, block erase, random program/read, ID read, status read, reset, and lock commands ECC:
* Hardware ECC (24 bits code Hamming Algorithm), 1-bit error correctable, 2-bit error
detection
* Reed Solomon from 1 to 4 bits
Copy-Back Programming and Cache Programming for performance enhancement CEn pin de-assertion during Flash busy and idle to save power consumption Two chip enables for interface to two NAND Flash devices
2.2.2.1
Write Operations
For write operations, erase the block before the write. The bus master first fills up the internal write buffer through the Write Data Registers (Table 113 p. 101). software then programs the Address registers and Data Length Register (Table 93 p. 94) to setup the address and data transfer length. It then programs the Control Register to setup the write command and other control parameters and starts the write operation. When the NAND Flash Controller receives the write command, it generates the necessary program command and address on the Flash bus, and writes the input data from the internal write buffer onto the Flash bus. Typically, the NAND Flash Controller should be allowed to finish programming the entire page. Refer to Section , NAND Flash Access Examples, on page 37 for a NAND Flash write example. If ECC check is enabled, the NAND Flash Controller must be allowed to program the entire page, and it will insert the computed ECC bytes at the end of the page.
2.2.2.2
Read Operations
For read operations, the software first programs the Address registers and Data Length Register (Table 93 p. 94) to setup the address and data transfer length. software then programs the Control Registers to setup the read command and other control parameters and then starts the read operation. When the NAND Flash receives the read command, it generates the necessary program command and address on the Flash bus. When read data is available, the NAND Flash Controller toggles the NF_REn signal to read the data from the Flash and puts the data into the internal read buffer. Typically, the NAND Flash Controller should be allowed to finish reading the entire page. The software waits for the interrupt and checks the field in the Status Register (Table 90 p. 93) then reads the data through the Read Data Registers (Table 112 p. 100). Refer to Section , NAND Flash Access Examples, on page 37 for a NAND Flash read example. If ECC check is enabled, the NAND Flash Controller must be allowed to read the entire page, and it will run the ECC correction scheme at the end of the page.
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Figure 5: NAND Flash Controller Block Diagram
NAND Interface Control Signals Bus Interface and Control Registers NAND Interface State Machine and Interface Signal Generator NAND Flash Device Signals
Bus Signals
Read Buffer
Write Buffer
ECC Checker and Generator Bootup Options
Figure 6: NAND Flash
IDLE if cmd_vld=1 and rdy =1 COMMAND CYCLE if do_addr_cyc=0 and rd=1 if do_addr _cyc=1 if wr=1 AD DRESS CYCLE if rd=1
if do_addr_cyc=0 and wr=1
READ CYCLE else back to ID LE W RITE CYCLE
W AIT FOR BU SY
if wait_for_bsy=1 if do_addr _cyc=0 and rd =0 & wr=0
NON-MEMOR Y READ
back to IDLE
System Data Flow
Data Storage All NAND Flash access starts with a command. Table 12 shows the command sets for Samsung Type 1 NAND Flash devices; Table 13 shows the command sets for Samsung Type 2 NAND Flash devices.
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Table 12: Samsung Type 1 NAND Flash Device Command Sets and Support
F la s h C o m m a n d Read 1 Read 2 Read ID Reset Page Program Copy_Back Program Lock Unlock Lock-tight Read Block Lock Status Block Erase Read Status 1 s t C yc l e ( h e x ) 0x00 / 0x01 0x50 0x90 0xFF 0x80 0x00 0x2A 0x23 0x2C 0x7A 0x60 0x70 0xD0 0x24 0x10 0x8A 2nd Cycle (hex) N FC S u pp o r t Yes Yes Yes Yes Yes Yes Yes Yes No Yes Yes Yes
Table 13: Samsung Type 2 NAND Flash Device Command Sets and Support
F la s h C o m m a n d Read Read for Copy Back Read ID Reset Page Program Cache Program Copy_Back Program Block Erase Random Data Input Random Data Output Read Status 1 s t C yc l e ( h e x ) 0x00 0x00 0x90 0xFF 0x80 0x80 0x85 0x60 0x85 0x05 0x70 0xE0 0x10 0x15 0x10 0xD0 2nd Cycle (hex) 0x30 0x35 N FC S u pp o r t Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
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ECC There are two types of ECC: Hamming (1or 2-bit)--Hardware is used. The whole page must be read to do ECC. When page read transfer is done, the field in the Read ECC Result Register (Table 102 p. 97) should be read determine if an error has occurred. If =0x0, no errors occurred. If =0x1, a 1-bit error occurred, and the field in the Read ECC Result Register (Table 102 p. 98) indicates the failed bit location. If =0x2, an uncorrectable error occurred. Reed-Solomon (4-bit), as shown in Figure 7--Hardware checks for error, and software corrects the error. The whole page must be read to do ECC. When page read transfer is done, field in the Read ECC Result Register (Table 102 p. 97)=0x0 indicates no errors occurred. If =0x1, software must read the RS ECC Decode Syndrome 0 and 1 Register (Table 106 p. 99) through RS ECC Decode Syndrome 6 and 7 Register (Table 109 p. 100) and run the 4-bit decoding algorithm to determine the error locations and error patterns. If using Hamming Code, depending upon page size (512 byte page or 2 KB page), perform either 515-byte read (page size + 3 byte) or 2051-byte read (page size + 3 byte). If using Reed-Solomon Code, depending on page size (512 byte page or 2 KB page), perform either 526-byte read (page size + 2 byte CRC + 12 byte ECC) or 2062-byte read (page size + 2 byte CRC + 12 byte ECC). Note: 2 byte CRC is always inserted and checked by hardware. Wait for read operation to complete. If using Hamming Code, check the field in the Read ECC Result Register (Table 102 p. 97). The field in the Read ECC Result Register (Table 102 p. 98) are only applicable when Hamming Code is used. If using Reed-Solomon Code, check the field in the Read ECC Result Register (Table 102 p. 97). The CRC can detect patterns that the RS-ECC cannot detect.
Figure 7: Reed-Solomon ECC Diagram
512 Byte Page
2 KB Page
512 Byte Data
2 KB Data
2 Byte CRC 12 Bytes RS-ECC
2 Byte CRC 12 Bytes RS-ECC
Concerns Regarding the Use of RDY Input from NAND Device
After each Program command, software can rely on the NAND RDY input to trigger an interrupt to signal the software to proceed to the next command. However, after each Block Erase command, software cannot rely on the NAND RDY input as a signal to proceed if the next command depends
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Functional Description
Functional Overview
on the completion of this particular Block Erase. This means if the software has issued a Block Erase command and received an Interrupt triggered by NAND RDY, the software can Program/Read pages other than the ones inside the block in question. To ensure the Block Erase has completed, software must periodically issue the Read Status command (a non-memory read) and see that the Status Ready bit is set in the return 8-bit status word.
NAND Flash Access Examples Data Transfer
Slave interface only--To read 250 bytes from column address 0x1abcd and row address 0x120 (data length and starting row address must not cross page boundary) of Samsung NAND Flash K9F2G08Q0M, the software must do the following: 1. Set field in the DMA Control Register (Table 103 p. 98) = 0. 2. Set Data Length Register (Table 93 p. 94) to decimal 250. 3. Set Control Register 2 (Table 88 p. 92) to 0x130. 4. Set Control Register (Table 87 p. 91) to 0xe4000000. 5. Wait for field in the Interrupt Register (Table 91 p. 93)= 1. 6. Retrieve 250 bytes of data through Read Data Registers (Table 112 p. 100). Slave interface only--To write 250 bytes to column address 0x1abcd and row address 0x120 (data length and starting row address must not cross page boundary) of Samsung NAND Flash K9F2G08Q0M, the software must do the following: 1. Set field in the DMA Control Register (Table 103 p. 98) = 0. 2. Set Data Length Register (Table 93 p. 94) to decimal 250. 3. Set Address Register (Table 94 p. 94) to 0x120 and Address Register 2 (Table 95 p. 95) to 0x1abcd. 4. Set Control Register 2 (Table 88 p. 92) to 0x20000110. 5. Set Control Register (Table 87 p. 91) to 0xe2000080. 6. Wait for field in the Interrupt Register (Table 91 p. 93)= 1. Master interface only--To read 250 bytes from column address 0x1abcd and row address 0x120 (data length and starting row address must not cross page boundary) of Samsung NAND Flash K9F2G08Q0M, the software must do the following: 1. Set field in the DMA Control Register (Table 103 p. 98) = 1 and field in the DMA Control Register (Table 103 p. 98) = 0. 2. Set DMA Address Register 0 (Table 104 p. 98) to desired address. 3. Set Data Length Register (Table 93 p. 94) to decimal 250. 4. Set Control Register 2 (Table 88 p. 92) to 0x130. 5. Set Control Register (Table 87 p. 91) to 0xe4000000. 6. Wait for field in the Interrupt Register (Table 91 p. 93). 7. Read data is completely transferred to set DMA Address. Master interface only--To write 250 bytes to column address 0x1abcd and row address 0x120 (data length and starting row address must not cross page boundary) of Samsung NAND Flash K9F2G08Q0M, the software must do the following: 1. Set field in the DMA Control Register (Table 103 p. 98) = 1 and field in the DMA Control Register (Table 103 p. 98) = 1. 1. Set DMA Address Register 0 (Table 104 p. 98) to desired address 2. Set Data Length Register (Table 93 p. 94) to decimal 250. 3. Set Address Register (Table 94 p. 94) to 0x120 and Address Register 2 (Table 95 p. 95) to 0x1abcd. 4. Set Control Register 2 (Table 88 p. 92) to 0x20000110. 5. Set Control Register (Table 87 p. 91) to 0xe2000080. 6. Wait for field in the Interrupt Register (Table 91 p. 93).
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Note
Software waits for field in the Interrupt Register (Table 91 p. 93) for read operation because DMA is the last step of read operation and waits for field in the Interrupt Register (Table 91 p. 93) for write operation because Command execution is the last step of write operation.
Read Status Command Each Flash device contains an 8-bit Status Register that can be read to determine whether a program or erase operation completed successfully. To issue a read status command, first set the field in the Control Register (Table 87 p. 92) to 0x70 (hex) and the field in the Control Register (Table 87 p. 91) to 0x1. Wait for the field in the Interrupt Register (Table 91 p. 93), then read the Non-Memory Read Data Register (Table 99 p. 97) for the status. Read ID Command Use this command to read the product identification code. Devices have
either a 2-byte or 4-byte ID. Follow the same flow as in the Read Status Command example, but set field in the Control Register (Table 87 p. 92) to 0x90 and the field in the Control Register (Table 87 p. 91) to obtain either 2-byte or 4-byte ID.
Reset Command The Flash device can be reset with the reset command. When the device is in
the Busy state during read/program/erase modes, the reset operation aborts the operation.
Lock/Unlock Command Some Flash devices provide Lock/Unlock commands to allow the
software to control which block is locked or unlocked. The lock command is typically applied to the entire Flash memory, and the unlock command allows a specific block or group of consecutive blocks to be unlocked.
Block Erase Command An erase operation sets all bits in the addressed block to 1s. To issue
a block erase command, first set the targeted block location in the corresponding Address Registers, then set the field in the Control Register 2 (Table 88 p. 92) to 0x1d0, then the field in the Control Register (Table 87 p. 92) to 0x60 and the number of address bits to device specific values and the field in the Control Register (Table 87 p. 91) to 1. Wait for device not busy, then issue a read status command to check the status of the block erase command just issued.
2.2.3
SDIO Host Controller
The SD host controller is a hardware block and acts as a host of the SD bus to transfer data between SD memory or SDIO cards and internal buffers and the internal bus master. One side of this block interfaces with a standard SD host bus. The other side internally interfaces with two programmable mode interfaces: DMA interface: In this mode, this block acts as an internal master which accesses the SDRAM using the DMA engine. CPU interface: The CPU accesses through the internal bus. This interface is most likely used for debugging purposes. Figure 8 shows the SDIO host controller block diagram.
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2.2.3.1
Features
1-bit/4-bit SDmem and SDIO High speed mode supported for SD at 48 MHz Supports interrupts for information exchange between host and cards Supports read wait control in SDIO cards Programmable internal interfaces Hardware generation/checking of CRC on all command and data transaction on the card bus True dual-port data FIFO (128x32) used as internal buffer. One side of the FIFO interfaces with the host bus. The other side is programmable to interface with a DMA engine or directly from the CPU. Suspend/resume in SDIO cards Card insertion/removal detection for SD cards Figure 8 shows the SDIO host block diagram.
Figure 8: SDIO Host Block Diagram
CL
Clock Control
Data Line Processing Bus DMA Interface Data FIFO CRC Check and CRC Generation Bus IRQ Registers and Command Sync Interrupt
DAT[3:0]
Command/Response Line
CMD
2.2.3.2
SD Bus Protocol Description
Communication over the SD bus is based on commands and data bit streams that are initiated by a start bit and terminated by a stop bit. Command: A command is a token that starts an operation. It is sent from the host to the card(s) and is transferred serially on the CMD line (1 bit). Command Response: A command response is a token that is sent from an addressed card to the host as an answer to a previously received host command. It is transferred serially on the CMD line since the CMD line is a bidirectional signal. Data: There are four data lines. Data can be transferred from the card to the host or vice versa. Data is transferred via Data line, and they are bidirectional signals. In 1-bit mode, SD_DATA[0] is used, and the other is in Z-state. Figure 9, Figure 10, and Figure 11 show basic operations of the SD cards.
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Figure 9: "No Response" and "No Data" Operation
From host to card From host to card From card to host
CMD DAT
Command
Command
Response
Operation (no response command )
Operation (no data )
Figure 10: Multiple Block Read Operation
From host to card From card to host From card to host From host to card From card to host
CMD DAT
Command
Response
Command
Response
Data Block Block read operation
CRC
Data Block
CRC Data stop operation
Multiple Block read operation
Figure 11: Multiple Block Write with Card Busy Operation
From host to card From card to host From host to card From host to card From card to host
C MD D AT
C ommand
R esponse D ata Block CRC
From card to host
C ommand D ata Block CRC
R esponse CRC Status
CRC Status
Busy
Block w rite operation Multiple Block w rite operation
D ata stop operation
2.2.3.3
Special Bus Transactions
Read Wait Command
The host usually stops the clock to stop the read data output from the card whenever the host cannot accept any more data. During the clock stop, the host capabilities are limited as it cannot issue commands during read. A Read Wait command allows the host to stop the read data while the clock is still on. A Read Wait command is issued after the data block end.
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Figure 12: Read Wait Controlled by Stopping Clock
SDCLK DATA Rd data 1a Rd data 1b
SDCLK DAT DAT[2] CMD Rd data 1a Rd data 1b
CMD52
Packet Format
Figure 13, Figure 14, Figure 15, and Figure 16 show the formats of commands from the host and responses from cards and data.
Figure 13: Command Token Format
Transmitter bit : 1 =host command Start bit Always 0 C ommand and addr . Info. or parameter End bit Alw ays 1
0
1
CONTEN T
CR C
1
48 bits
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88ALP01 Datasheet
Figure 14: Response Token Format
Transmitter bit : 0=card response Start bit Always 0 Response from card End bit Always 1
0
0
CONTENT 48 bits
CRC
1
0
0
CONTENT 136 bits
CRC
1
Figure 15: Data Packet Format, Standard Bus (Only DAT0 Used)
Start bit Always 0 MSB
LSB
End bit Always 1
0
4095 Block length
0
CRC
1
Figure 16: Data Packet Format, Wide Bus (All Four Data Lines Used)
0 0 0 0
4095 4094 4093 4092 Block length /4
3 2 1 0
CRC CRC CRC CRC
1 1 1 1
Sequences of Host and Card Interaction
SD cards are connected to the host with a dedicated interface, such as its own CLK, CMD, or DATA lines.
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The host and SD cards go through two phases after power on reset, software reset, or if a new card is plugged in: Card identification phase: The host looks for new cards on the bus. While in this phase, the host resets all the cards that are in card identification mode. Any card already identified will not be reset. Then the host sends the command to validate operation voltage range, identifies cards and asks them to publish the Relative Card Address (RCA). This operation is done to each card separately on its own CMD line in the case of SD memory,. All data communication in the Card Identification phase uses the CMD line only. Data transfer phase: The host enters this phase after identifying all the cards on the bus. In this phase, the host is ready to transfer data. After the host driver sets up the host controller, it starts the transfer by writing to the Command Register, which is written last. The host initialization flow chart is shown in Figure 17.
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Figure 17: Host Initialization Flow Chart
Idle State
Response ACMD41 (arg=00)
No Response
CMD0 (Reset Card)
Response Non-SD Memory/ SDIO Card CMD1
No Response
CMD5 Response
No Response
SD Memory Card Ready State
SDIO Card Ready State
CMD2
Identification State
Identification State
CMD3
CMD3 Card Identification Phase
Data Transfer Phase Standby State Standby State
CMD3
CMD7
2.2.3.4
Card Detection
The 88ALP01 design supports card detection (insertion/removal) based on the card detect switch level on the SD socket. This card detection features can be accessed though the Normal Interrupt Status Enable bits. If this feature is enabled, an interrupt is generated when a logic change is detected on the card detect switch input. This logic change is debounced before generating an interrupt.
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2.2.4
2.2.4.1
CMOS Camera Interface Controller
Features
Still images up to 2.0 Megapixels Interfaces:
* Parallel input: interface support for 8 bits * Supports embedded hsync/vsync format (BT-656)
Capture modes:
* * * * * * * * *
RGB 4:4:4 RGB 5:5:5 RGB 5:6:5 YCbCr 4:2:2
Raw capture modes: Bayer Output formats: YCbCr 4:2:2 (planar and packed) Raw Bayer packed: 8-bit/pix (4-pix in 32-bit) RGB 16-bit/pix (4:4:4, 5:5:5, 5:6:5)
YCbCr 4:2:0 (planar) Frame buffers in system memory with up to three ping-pong buffers Interrupts (interrupts are optional, system can work with all interrupts masked out)
* Frame-start * Frame-end * FIFO overrun
2x downscale on YCbCr and RGB output formats
2.2.4.2
I/O Signals
The CCIC chip-level I/O signals are described in Table 14.
Table 14: CCIC Chip-Level I/O Signal Descriptions (2.5V or 3.3V)
P in N a m e HSYNC VSYNC PIXDATA[7:0] PIXCLK PIXMCLK SENSOR_CTL0 SENSOR_CTL1 TWSI_SCLK TWSI_SDATA P in Typ e I/O I/O I I O O O O I/O I /O Typ e CMOS 2.5V or 3.3V CMOS 2.5V or 3.3V CMOS 2.5V or 3.3V CMOS 2.5V or 3.3V CMOS 2.5V or 3.3V CMOS 2.5V or 3.3V CMOS 2.5V or 3.3V CMOS 2.5V or 3.3V Open Drain D e fi n it io n Horizontal Sync driven by external CMOS sensor Vertical Sync driven by external CMOS sensor Pixel Data Synchronous to PIXCLK. Pixel Clock Pixel Master Clock Sensor Control 0 Sensor Control 1 TWSI Serial Clock TWSI Serial Data
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88ALP01 Datasheet
Figure 18: CCIC Block Diagram
CMOS SENSOR
BT-656
Downscale
MUX
Data Formatter
FIFO
DMA
Config. Registers
Internal Master Bus
Slave Bus
2.2.4.3
Interface Modes
Table 15: Supported Interface Modes
D a ta B us Wi dth 8-bit 8-bit h s yn c a n d vsync Yes No D e sc r ip ti on s External CMOS Sensor drives PIXCLK, HSYNC, VSYNC, and PIXDATA[7:0] External CMOS Sensor drives PIXCLK and PIXDATA[7:0]. Start-of-Active-Video (SAV) and End-of-Active-Video (EAV) are encoded in the data stream.
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2.2.4.4
Input/Output Matrix
Table 16 shows the color I/O matrix.
Table 16: Color I/O Matrix
In p u t RGB 5:6:5 YCbCr 4:2:2 RGB 4:4:4 RGB 5:5:5 Raw Bayer 8-bit O u tp u t RGB 5:6:5 YCbCr 4:2:2 YCbCr 4:2:0 ARGB 4:4:4:4 ARGB 1:5:5:5 Raw Bayer N ot e RGB Endianness is programmable. YCbCr 4:2:2 output can be packed or planarized. Alpha value and RGB Endianness are programmable. Alpha value and RGB Endianness are programmable. Raw Bayer pixels are packed into 32-bit.
2.2.4.5
Video Timing Reference Codes (SAV and EAV)
This section is derived from the ITU-R BT.656-R specification, section 2.4. There are two timing reference signals: SAV, which occurs at the beginning of each video data block EAV, which occurs at the end of each video data block Each timing reference signal consists of a four-word sequence in the following format: FF 00 00 XY. (Values are expressed in hexadecimal notation. FF 00 values are reserved for use in the timing reference signals.) The first three words are a fixed preamble. The fourth word contains information defining field two identification, the state of field blanking, and the state of line blanking. The bit assignments within the timing reference signal are shown in Table 17.
Table 17: Video Timing Reference Codes
D a ta B it Number 7 6 5 4 3 2 1 0 1 s t Wo r d ( F F ) 1 1 1 1 1 1 1 1 2 n d Wo r d (00) 0 0 0 0 0 0 0 0 3r d Wo r d ( 0 0 ) 0 0 0 0 0 0 0 0 4 t h Wo r d ( X Y ) 1 F V H P3 P2 P1 P0
Bits P0, P1, P2, and P3, have states dependent on the states of the bits F, V, and H, as shown in Table 18. At the receiver, this arrangement permits correction of 1-bit errors and detection of 2-bit errors.
Table 18: Bits States
F 0 0 0 V 0 0 1 H 0 1 0 P3 0 1 1 P2 0 1 0 P1 0 0 1 P0 0 1 1 D e s c r ip t i o n s SAV: Field 1 Active Video EAV: Field 1 Active Video SAV: Field 1 Blanking
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Table 18: Bits States (Continued)
F 0 1 1 1 1 V 1 0 0 1 1 H 1 0 1 0 1 P3 0 0 1 1 0 P2 1 1 0 1 0 P1 1 1 1 0 0 P0 0 1 0 0 1 D e s c r ip t i o n s EAV: Field 1 Blanking SAV: Field 2 Active Video EAV: Field 2 Active Video SAV: Field 2 Blanking EAV: Field 2 Blanking
The CCIC starts capturing data when it detects either one of the following sequences: 1. 2. 1. 2. FF 00 00 80 (SAV: Field 1 Active Video) FF 00 00 C7 (SAV: Field 2 Active Video) FF 00 00 9D (EAV: Field 1 Active Video) FF 00 00 DA (EAV: Field 2 Active Video)
It stops capturing data when it detects either one of the following sequences:
2.2.4.6
RGB Input Data Formats
The following tables provide the RGB and YCbCr input data formats: Table 19 for 8-bit RGB 5:6:5 Table 20 for 8-bit YCbCr 4:2:2
Table 19: 8-bit RGB 5:6:5 Input Data Format
P ix d a ta B it Number 7 (MSB) 6 5 4 3 2 1 0 (LSB) Byte Sequence Pixel R G B 5 : 6 : 5 B y t e S eq u e n c e G0[2] G0[1] G0[0] R0[4] R0[3] R0[2] R0[1] R0[0] 0 0 B0[4] B0[3] B0[2] B0[1] B0[0] G0[5] G0[4] G0[3] 1 G0[2] G0[1] G0[0] R1[4] R1[3] R1[2] R1[1] R1[0] 2 1 B1[4] B1[3] B1[2] B1[1] B1[0] G1[5] G1[4] G1[3] 3 G2[2] G2[1] G2[0] R2[4] R2[3] R2[2] R2[1] R2[0] 4 2 B2[4] B2[3] B2[2] B2[1] B2[0] G2[5] G2[4] G2[3] 5
Table 20: 8-bit YCbCr 4:2:2 Input Data Format
P ix d a ta B it Number 7 (MSB) 6 YCbCr 4:2:2 Byte Sequence Cb0[7] Cb0[6] Y0[7] Y0[6] Cr0[7] Cr0[6] Y1[7] Y1[6] Cb1[7] Cb1[6] Y2[7] Y2[6]
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Functional Overview
Table 20: 8-bit YCbCr 4:2:2 Input Data Format (Continued)
P ix d a ta B it Number 5 4 3 2 1 0 (LSB) Byte Sequence Y Pixel Cb, Cr Pixel YCbCr 4:2:2 Byte Sequence Cb0[5] Cb0[4] Cb0[3] Cb0[2] Cb0[1] Cb0[0] 0 0 0 and 1 Y0[5] Y0[4] Y0[3] Y0[2] Y0[1] Y0[0] 1 Cr0[5] Cr0[4] Cr0[3] Cr0[2] Cr0[1] Cr0[0] 2 1 Y1[5] Y1[4] Y1[3] Y1[2] Y1[1] Y1[0] 3 Cb1[5] Cb1[4] Cb1[3] Cb1[2] Cb1[1] Cb1[0] 4 2 2 and 3 Y2[5] Y2[4] Y2[3] Y2[2] Y2[1] Y2[0] 5
2.2.4.7
CCIC Recommended Programming Sequence
1. Configure external CMOS sensor resume and power down modes:
* Configure SENSOR_CTL0 pin to 0 to put external CMOS sensor in reset mode. * Configure SENSOR_CTL1 pin to 1 to put external CMOS sensor in power-down mode. * Program the General Purpose (GPR) Register (Table 180 p. 137) to 0x32.
2. Power up external CMOS sensor:
* Program Global Register 0x3058 bit [3] = 1. * Program Global Register 0x315C bit [19] and bit [3] to 1. * Allow some time for voltage to ramp up.
3. 4. 5. 6. 7. 8. 9. Configure CCIC in normal mode by programming the field in the Control 1 Register (Table 176 p. 135) = 0. Release external CMOS sensor reset and power down.
* Program General Purpose (GPR) Register (Table 180 p. 137) to 0x31.
Configure external CMOS sensor input clock by programming the Clock Control Register (Table 177 p. 136). Configure TWSI Control 0 Register (Table 181 p. 138). Configure external CMOS sensor registers through TWSI Control 1 Register (Table 182 p. 139). Either polling mode or interrupt mode can be used. Configure CCIC (video buffer addresses, video modes, etc.), while keeping field in the Control 0 Register (Table 175 p. 135) = 0. Enable CCIC DMA.
* Program = 1.
2.2.5
VPD Serial EEPROM
The serial EEPROM is an external memory device for application-dependent configuration data and Vital Product Data (VPD). Its address space is divided into two parts as shown in Figure 19.
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Figure 19: Internal Structure of Serial EEPROM
address max. 2 KB Configuration normal configuration data (read only) organized in 8 byte blocks
256 255 128 127 0
VPD writable VPD
VPD Threshold = 1
VPD read only
The VPD data is located within the lower address region (0 to 255). This data contains the read only and writable section of VPD separated by VPD Threshold. The normal configuration data are stored in higher EEPROM addresses. Following RSTn, if enabled, the 88ALP01 uses its internal serial EEPROM Loader to load these data automatically. The VPD serial EEPROM is read from and written to via the VPD TWSI bus at TWSI address 0b101000. A serial EEPROM such as Atmel's AT24C02 or equivalent may be used. For manufacturing programming of the read only part of the serial EEPROM, testmode (En Config Write) must be set. Then the whole serial EEPROM is writable. Programming of the serial EEPROM is managed with ASIC internal registers, VPD Address Register (Table 58 p. 75) and VPD Data Registers (Table 59 p. 76). After the next power cycle, the read only areas within the serial EEPROM are write protected again.
2.2.5.1
VPD Serial EEPROM Loader
The Serial EEPROM Loader accesses the external serial EEPROM for configuration data. The serial EEPROM Loader is active after RSTn if enabled. Startup data is loaded out of the serial EEPROM into Configuration and Control Register File. Serial EEPROM load is for loading startup data into the Configuration and Control Register File (where needed):
* The loader is capable of accessing potentially all registers in the Control Register File space. * The register address and data are stored in 8-byte entries in the Serial EEPROM. * The 8-byte entries are located on 8-byte boundaries up from address 256 of the serial
EEPROM in increasing order. Each entry is marked with a key byte (0x55).
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Functional Overview
Table 21: Data Format of First 8 byte Block within Serial EEPROM
T W S I A c c es s Cycle Number 2 S e r ia l E E PR O M Address 0x107 0x106 0x105 0x104 1 0x103 0x102 0x101 0x100 Content Data<3> Data<2> Data<1> Data<0> Address/upper Bit [7:2]: Address/lower Bit [1:0]: Function number Bit [7:4]: Opcode Bit [3:0]: CBEn[3:0] Key = 0x55
The ASIC internal registers may be written with dword, word, or byte accesses. The loader, if started, reads subsequent entries starting with the initial value of the serial EEPROM address counter as long as a valid key is found. Loading is started right after reset or by setting the flag to start the Serial EEPROM Loader. The Flag in the serial VPD Serial EEPROM Loader Control Register (Table 60 p. 76) is intended for testing purposes only. Reloading the Configuration Register File using this command is not recommended. Accesses to any resource of the 88ALP01 are terminated by Target Retry Cycles while loading. The data transferred after RSTn in this way is limited to fulfilling the requirements of the PCI bus. Trhfa RSTn High to First configuration Access is limited to 225 clock cycles. PCI clock 66 MHz: Trhfa = 0.5 s -> max. 5.6 KB PCI clock 33 MHz: Trhfa = 1 s -> max 2.8 KB This reading via TWSI bus may be deactivated during RSTn. Transformation of the serial EEPROM data (8 bytes) into multiple byte/dword memory read accesses from the bus.
* The 8-byte serial EEPROM data is loaded over the TWSI-Bus using multiple byte/dword
memory read accesses. For example, one 64-bit internal register write requires two 32-bit bus reads of the EEPROM contents through the bus.
2.2.5.2
VPD Two-Wire Serial Interface
The VPD TWSI is controlled either by software with the Interface Register or by hardware with the VPD TWSI (HW) Control Register (Table 82 p. 88) and the VPD TWSI (HW) Data Register (Table 83 p. 89). If hardware-controlled TWSI accesses are used, the Interface Register must be set to inactive values (Clock = 1, Direction = 0, Data = 0). The hardware controlled interface can be controlled in different ways. The size of the target device of the VPD TWSI access (and implicitly the number of address bytes/bits to be used) and its devsel byte, together with the address, must be written to the VPD TWSI (HW) Control Register (Table 82 p. 88). If the TWSI Burst bit is set, the TWSI runs four byte bursts in page mode, assuming pages of eight bytes. Invalid or erroneous HW controlled TWSI accesses that are not completed, can be stopped by writing a one to TWSI Stop. On completion of a hardware controlled TWSI access an interrupt IRQ TWSI Ready is asserted.
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The VPD TWSI connects to an EEPROM that utilizes VPD as suggested by PCI Rev. 2.3. VPD is stored in a serial EEPROM and may be accessed through the VPD Address Register (Table 58 p. 75) and VPD Data Registers (Table 59 p. 76). These registers are mapped writable both into configuration and I/O address space.
2.2.6
Device Reset
The 88ALP01 supports PCI power management. When in Sleep mode, PCI reset may be active but parts of the device observe SD card assertion for wake up event. The 88ALP01 is completely reset by the "power on reset". The PCI reset is applied to all logics except the PCI sleep control (PME) and wake up parts.
2.2.7
Reset Configuration
The 88ALP01 uses the following pins as configuration inputs to set parameters following a power-on reset. The definition of these pins change immediately after power-on reset to their normal function.
Note
To set a configuration bit to 0, attach a 10 k resistor from the appropriate pin to ground. No external circuitry is required to set a configuration bit to 1.
Table 22: 88ALP01 Configuration Pins
C o n fi gu r a t io n B i ts CON[7] 88 A L P 0 1 P i n VPD_CLK C o nf ig u r a ti on Fu n c ti on 66 MHz PCI capability 0 = Capability is not present 1 = 66 MHz PCI capability present Reserved for future use PLL Bypass Disable 0 = PLL bypass enabled 1 = PLL bypass disabled EEPROM Load Disable 0 = Load enabled 1 = Load disabled
CON[6:2] CON[1]
Reserved NF_DATA[1]
CON[0]
NF_DATA[0]
2.2.8
Clock Generation/Distribution
There are two main clock domains in the 88ALP01 (not counting divided down clocks in sub modules). The PCI section driven with PCI CLK (0 to 66 MHz) The core logic is driven with core clock generated by on chip PLL from 24 MHz external reference. The PCI Clock is driven from PCI and runs all state machines and registers which have to be synchronous with the PCI Clock, that is, the Master and Target state machines and the PCI Configuration Registers. This group also includes the external VPD TWSI.
2.2.9
PME on Wake up event
The 88ALP01 can be configured to assert the PMEn signal under the following conditions:
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Functional Description
Functional Overview
PCI bus in sleep mode with VDDO still applied (D3-hot) SD card is inserted, removed or SD card asserts an interrupt
2.2.9.1
Power Management Support
The 88ALP01 supports power management as defined in the PCI Bus Power Management Interface Specification v1.1. The PCI power management interface includes the capabilities data structure and power management register block definitions. When the system is in a power-down mode, PCI bus power is on, the PCI clock may be slowed down or stopped, and the wake-up output pin may drive the PME pin on the PCI bus to cause the hardware on the system device to put the computer into the working (D0) mode. The device only supports SD card insertion wake-up event.
2.2.9.2
PCI Device Power States
The 88ALP01 function 1 supports all of the following PCI device power states, as defined in Table 23. Function 0 and function 2 only support D0 and D3hot.
Table 23: Device Power Status
D e v i c e Sta t e D0 (Fully On)1 VDDO On P C I C lo c k Free running Bus PCI A c t iv i t y Any PCI transaction, function, interrupt, or PME event PME event, config cycles PME event, config cycles PME event, config cycles F u nc ti o n S up p o r t Function 0, 1, and 2
D1 D2 D3hot
On On On
Free running Free running or stopped Free running or stopped
Function 1 Function 1 Function 0, 1, and 2
1. In the D0 state, all hardware on the 88ALP01 is fully functional.
In the D1, D2, and D3hot states, the PCI bus activities are restricted to config cycles and PME events. If a wake-up event occurs, the PME signal is raised under hardware control. The 88ALP01 does not require a PCI clock to generate a PME.
2.2.9.3
Wake-Up Sequence
The system software enables the PME pin by setting the field in the Power Management Control/Status Register (Table 53 p. 73) to 1. When a wake-up event is detected, the 88ALP01 sets the PME_STATUS bit in the PMCSR register (PCI configuration registers, field in the Power Management Control/Status Register (Table 53 p. 73)). Setting this bit causes the PME signal to be asserted. Assertion of the PME signal causes external hardware to wake up the host system CPU. The host system software then reads the PMCSR register of every PCI device in the system to determine which device asserted the PME signal. When the host software determines that the signal was caused by the 88ALP01, it writes to the 88ALP01 PMCSR to put the device into power state D0. This software then writes a ONE to the PME_STATUS bit to clear the bit and turn off the PME signal, and it calls the device's software driver to tell that the device is now in state D0. The system software can clear the PME_STATUS bit either before, after, or at the same time as the 88ALP01 is put back into the D0 state.
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2.2.10
Clock Run (CLK_RUNn)
The CLK_RUNn pin conforms with the Clock Run specification as described in the PCI Mobile Design Guide Revision 1.1. The CLK_RUNn pin is used for stopping and starting the PCI clock. The following is a list of conditions that trigger a request (via CLK_RUNn) for the clock to be restarted. The 88ALP01 attempts to maintain the PCI clock under the following conditions even if the central resource tries to stop or slow it down. The 88ALP01 has active PCI transactions. The device has received fewer than 20 PCI clocks after hardware reset is deasserted. Configuration from the Serial EEPROM is being loaded. Any of the three bus master (DMA) units (from all 3 functions) are not idle.
2.2.11
Power on Reset Delay
Upon power up, the 88ALP01 has an internal POR counter to extend the POR for more than 21.67 ms based on a 24 MHz reference clock. It is triggered by voltage crossing a pre-determined threshold and is intended to cause the 88ALP01 to wait for power to stabilize before releasing the reset at power up. The counter is counting on input reference clock; therefore, an increase in reference clock speed would decrease this POR delay.
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Register Description
Registers Introduction
3
3.1
Register Description
Registers Introduction
The registers included in this section are:
* * * * *
PCI Configuration Register File Global Control Registers NAND Flash Unit SDIO Host Controller Registers CMOS Camera Interface Controller Register maps are provided at the start of each register section.
3.1.1
Register Conventions
Figure 20 shows how to read the register tables in the register map.
Figure 20: Register Conventions
Register name Table number
Register Offset in hexadecimal
Table 25: Bits
7
Software Reset Offset: 0x02 Field
Reserved RSTn
Type/ HW Rst
Description
Reserved Title 0 = Software reset This register is initialized by power-on reset and the HW RESETn pin. The chip stays in the reset condition until RSTn is changed back to 1.
RSVD RW 0x01
Detail
6:0
Register type/ Hardware Reset value in hex
The registers in the 88ALP01 are made up of one or more fields. The way in which each of these fields operate is defined by the field's Type. The function of each Type is described in Table 24.
Table 24: Register Type Definitions
Ty p e EXEC ROC RSVD RO RW RW1C D e s c r i p t io n Execution of this command if appropriate bit is set Read on clear Reserved for future use. All reserved bits are read as zero unless otherwise noted. Read only. Read and Write.
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Table 24: Register Type Definitions (Continued)
Ty p e SH WO W1AC D e s c r i p t io n Special Handling as described Write only. Reads to this type of register field return undefined data.
The following conventions are used: * Commands (single bit) in Control Registers:
- - * - - - * - - - -
Commands are executed, if appropriate bit is set
Read value as defined. Exclusive commands (xxx Start/Stop, xxx On/Off): Commands are executed, if appropriate bit is set to 1. Setting both commands to 1, has no effect.
Status is readable: 0x1 or 0x2. Reset Value: = fixed value or value directly from input pin = reset to only by Power on and HW Reset (HW) = reset to only by Power on and HW Reset (SW) = reset to by Power on, HW Reset and SW Reset
3.2
PCI Configuration Register File
Providing configuration information and supporting access to configuration information is mandatory for any PCI adapter. This data is available in the PCI Configuration Register File. The Vital Product Data (VPD) implemented in the 88ALP01 is an optional PCI extension attached to the Configuration Register File. The implementation follows an Engineering Change Request (ECR) according to the PCI Specification Revision 2.2. PCI Power Management information and Vital Product Data are the PCI "New Capabilities" implemented in this adapter. The PCI Configuration Register File holds information about the PCI adapter for a smooth integration into the PCI bus system. The file holds data to identify the PCI adapter, about the I/O and memory requirements, and about other system resources needed, that is, interrupt lines and maximum power consumption. For read/write accesses, the configuration space is physically located in the ASIC. Its default/start values can be loaded from the VPD serial EEPROM by the VPD serial EEPROM Loader during startup with the exception of the Vital Product Data that is located in TWSI EEPROM as required by the PCI ECR. It is read through a VPD address port in the PCI configuration register file. The configuration registers are set to their default values by RSTn. Reloading out of the VPD serial EEPROM is initiated with the deassertion of RSTn if strapping input for EEPROM loading is set. The 88ALP01 device supports the 256-byte configuration space as defined by the PCI Specification Revision 2.2.
3.2.1
Configuration Data Access
The configuration space of a PCI adapter is usually accessed by using BIOS routines as described in the PCI BIOS specification. The configuration space of a adapter, for example, is addressed by selecting the IDSEL (detected by reading the unique DeviceID) plus an address in the 256 bytes configuration space address range. This is translated into Configuration Read / Configuration Write cycles executed on the PCI bus hardware level.
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Register Description
PCI Configuration Register File
The 88ALP01 responds to type 0 configuration accesses, i.e. AD[1:0] = "00", IDSELn asserted. The Configuration Register File can be accessed with 8-, 16-, or 32-bit transfers. On read transactions, all data is driven as defined for full 32-bit accesses independent of CBEn[3:0]. All multi-byte numeric fields follow little-endian order, if accessed by PCI configuration cycles. Write operations to reserved or not implemented registers are completed normally on the bus and the data is discarded. If the configuration space is targeted for a burst operation, it responds with a disconnect with the first data transfer. Configuration transactions are not aborted (Target Initiated Termination). Read operations to reserved or not implemented registers are completed normally on the bus and a data value of 0 is returned.
3.2.2
PCI Header Region
Table 25 depicts the layout of the configuration space of one of the three functions implemented in the 88ALP01, this 256-byte configuration space has been implemented separately for each of the three functions. Besides the mandatory configuration information in the configuration space header, the 88ALP01 provides access to two 32-bit registers called Access Control Register and VPD Control Register in the device dependent region of the adapter's configuration space. These registers contain information that is only important for initialization and not for the "run-time" driver tasks. Table 26 shows the address map of the configuration space in a 32-bit (maximum access width for configuration data) register representation.
Table 25: PCI Header Region Overview
R e g is t e r N a m e Header Portion Device ID Status Class Code BIST Base Address (1st) Reserved Subsystem ID Reserved Reserved Reserved Max_Lat Reserved Device Dependent Region SD Slot Information Register Access Control VPD Control Power Management Capabilities Power Management Next Item Pointer Power Management Capability ID 0x40 0x80 0x84 0x88 Min_Gnt Interrupt Pin Interrupt Line New Capabilities Pointer Subsystem Vendor ID Base-Class Latency Timer Vendor ID Command Revision ID Cache Line Size 0x00 0x04 0x08 0x0C 0x10 0x14 to 0x2B 0x2C 0x30 0x34 0x38 0x3C 0x41 to 0x7C Offset
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Table 25: PCI Header Region Overview (Continued)
R e g is t e r N a m e Power Management Data VPD Address VPD Data VPD Serial EEPROM Loader Control MSI Message Control MSI Message Lower Address MSI Message Upper Address MSI Message Data Reserved Calibration Control Register Discard Counter Register Reserved Calibration Status Register Retry Counter Register Reserved MSI Next Item Pointer MSI Capability ID (MSI Cap ID) Reserved Power Management Control/Status VPD Next Item Pointer VPD Capability ID Offset 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC to 0xB0 0xB4 0xB8 0xBC to 0xFC
Table 26: PCI Header Region Register Map
R e g is t e r N a m e Vendor ID Register Device ID Register Command Register Status Register Revision ID Register Programming Interface Register, Lower Byte Sub-Class Register, Middle Byte Base-Class Register, Upper Byte Cache Line Size Register Latency Timer Register Base-Class Register Built-in Self Test Register Base Address Register (1st) Reserved Subsystem Vendor ID Register Subsystem ID Register Reserved New Capabilities Pointer Register Reserved Interrupt Line Register Interrupt Pin Register Min_Gnt Register Offset 0x00 0x02 0x04 0x06 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x1C to 0x28 0x2C 0x2E 0x30 0x34 0x38 0x3C 0x3D 0x3E Ta b l e a n d P a ge Table 27, p. 60 Table 28, p. 60 Table 29, p. 60 Table 30, p. 62 Table 31, p. 63 Table 32, p. 63 Table 33, p. 63 Table 34, p. 63 Table 35, p. 64 Table 36, p. 64 Table 37, p. 65 Table 38, p. 65 Table 39, p. 65 -Table 40, p. 66 Table 41, p. 66 -Table 42, p. 67 -Table 43, p. 67 Table 44, p. 67 Table 45, p. 68
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Register Description
PCI Configuration Register File
Table 26: PCI Header Region Register Map (Continued)
R e g is t e r N a m e Max_Lat Register SD Slot Information Register Access Control Register VPD Control Register Power Management Capability ID Register Power Management Next Item Pointer Power Management Capabilities Register Power Management Control/Status Register Power Management Data Register VPD Capability ID Register VPD Next Item Pointer VPD Address Register VPD Data Registers Reserved VPD Serial EEPROM Loader Control Register MSI Capability ID Register (MSI Cap ID) MSI Next Item Pointer Register MSI Message Control Register MSI Message Lower Address Register MSI Message Upper Address Register MSI Message Data Register Calibration Control Register Calibration Status Register Discard Counter Register Retry Counter Register Offset 0x3F 0x40 0x80 0x84 0x88 0x89 0x8A 0x8C 0x8F 0x90 0x91 0x92 0x94 0x58 0x9A 0x9C 0x9D 0x9E 0xA0 0xA4 0xA8 0xB4 0xB6 0xB8 0xBA Ta b l e a n d P a ge Table 46, p. 68 Table 47, p. 69 Table 48, p. 69 Table 49, p. 70 Table 50, p. 71 Table 51, p. 71 Table 52, p. 72 Table 53, p. 73 Table 54, p. 74 Table 56, p. 75 Table 57, p. 75 Table 58, p. 75 Table 59, p. 76 -Table 60, p. 76 Table 61, p. 76 Table 62, p. 77 Table 63, p. 77 Table 64, p. 78 Table 65, p. 78 Table 66, p. 79 Table 67, p. 79 Table 68, p. 80 Table 69, p. 80 Table 70, p. 80
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3.2.2.1
Vendor ID Register
The Vendor ID Register comprises 16 bits.
Table 27: Vendor ID Register
Offset: 0x00
B its 15.0 F ie l d Vendor ID Ty p e / I n it Va l RO 0x11AB D e s c r i p t io n Identifies manufacturer of the device (Marvell)
3.2.2.2
Device ID Register
The Device ID Register comprises 16 bits that uniquely identifies the device within the product line. It is reloadable from the VPD serial EEPROM.
Table 28: Device ID Register
Offset: 0x02
B its 15:0 F ie l d Device ID Ty p e / I n it Va l D e s c r ip t i o n
Identifies the device within the product line RO Function 0: 0x4100 Function 1: 0x4101 Function 2: 0x4102
3.2.2.3
Command Register
The Command Register comprises 16 bits. It is used to control the overall functionality of the adapter. It controls the adapter's ability to generate and respond to PCI bus cycles. To disconnect the adapter logically from all PCI bus cycles except the configuration cycles, a value of ZERO should be written to this register. All bits are reloadable from the VPD serial EEPROM, except for fixed value bits.
Table 29: Command Register
Offset: 0x04
B its 15:11 10 F ie l d Reserved INTDIS Ty p e / I n it Va l RSVD RW 0 D e s c r i p t io n Reserved for future use Disable asserting INT 1 = INT is disabled 0 = INT is enabled
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Register Description
PCI Configuration Register File
Table 29: Command Register (Continued)
Offset: 0x04
B its 9 F ie l d FBTEN Ty p e / I n it Va l RW 0 D e s c r i p t io n Fast Back-to-Back enable 1 = fast back-to-back transactions to different agents are allowed (adapter as master runs fast back-to-back write cycles). 0 = fast back-to-back transactions are only allowed to the same agent (adapter as master does not run fast back-to-back write cycles). SERRn enable, controls the assertion of SERRn pin 1 = SERRn is enabled 0 = SERRn is disabled Address/Data Stepping Fixed value adapter does not use address/data stepping. Parity Report Response Enable 1 = Parity error reporting is enabled. VGA Palette Snoop Fixed value Memory Write and Invalidate Cycle Enable 1 = Memory Write and Invalidate Cycle is enabled. 0 = Memory Write must be used instead. Special Cycle Enable Fixed value adapter ignores all Special Cycle operations. Bus Master Enable 1 = bus master accesses are enabled. 0 = bus master accesses are disabled. Memory Space Access Enable 1 = memory accesses are responded. 0 = memory accesses are not responded. I/O Space Access Not Supported
8
SERREN
RW 0 RO 0 RW 0 RO 0 RW 0 RO 0 RW 0 RW 0 RO 0
7
ADSTEP
6 5 4
PERREN VGASNOOP MWIEN
3
SCYCEN
2
BMEN
1
MEMEN
0
IOEN
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88ALP01 Datasheet
3.2.2.4
Status Register
The Status Register comprises 16 bits. It contains status information for the PCI bus related events. Reads to this register behave normally. Writes are different, that is, bits can be reset but not set. A bit is reset whenever the register is written, and the data in the corresponding bit location is ONE. This behavior is marked with SH, special handling in the table below. All bits are reloadable from the VPD serial EEPROM, except for fixed value bits.
Table 30: Status Register
Offset: 0x06
B its 15 F ie l d PERR Ty p e / I n it Va l SH 0 SH 0 SH 0 SH 0 RSVD RO 01b SH 0 RO 1 RO 0 RO 1 D e s c r i p t io n Parity Error Is set whenever a parity error is detected (data or address), even if parity error handling is disabled (PERREN) Signaled SERRn Is set whenever an address parity error is detected and both, SERREN and PERREN are enabled Received Master Abort Is set when a master transaction is terminated with a master abort sequence Received Target Abort Is set when a adapter's master transaction is terminated with a Target Abort sequence Reserved for future use DEVSELn Timing Fixed value = 01b (medium), DEVSELn is asserted two CLK periods after FRAMEn is asserted Data Parity Error Detected Set, if a data parity error is detected running master cycles and PERREN is set Fast Back-to-Back Capable Fixed value = 1, target is capable of accepting fast back-to-back transactions UDF supported 66 MHz PCI Bus Clock Capable (see section 66 MHz Operation) The default value for this field can be changed by strapping input. New Capabilities Bit New capabilities list implemented Reserved for future use
14
SERR
13
RMABORT
12
RTABORT
11 10:9
Reserved DEVSEL
8
DATAPERR
7
FB2BCAP
6 5
UDF 66MHZCAP
4 3:0
NEWCAP Reserved
RO 1 RSVD
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Register Description
PCI Configuration Register File
3.2.2.5
Revision ID Register
The Revision ID Register comprises 8 bits. It is reloadable from the VPD serial EEPROM.
Table 31: Revision ID Register
Offset: 0x08
B its 7:0 F ie l d Revision ID Ty p e / I n it Va l RO 0x10 D e s c r i p t io n Specifies the adapter revision number/Rev. 1.0.
3.2.2.6
Class Code Register
The Class Code Register comprises 24 bits. This register is used to identify the generic function of the adapter. The register is broken down into three byte-size fields. One of these fields, the Subclass Register, is reloadable from the VPD serial EEPROM.
Table 32: Programming Interface Register, Lower Byte
Offset: 0x09
B its 7:0 F ie l d Ty p e / I n it Va l RO 0x01 D e s c r i p t io n Specifies the programming interface. Fixed Value = 0x01
Table 33: Sub-Class Register, Middle Byte
Offset: 0x0A
B its 7:0 F ie l d Ty p e / I n it Va l RO Function 0: 0x01 Function 1: 0x05 Function 2: 0x00 D e s c r ip t i o n Identifies the Function0 Controller 0x01 = Identified as Flash memory Controller 0x05 = Identified as SD Host controller 0x00 = Identified as Video Controller
Table 34: Base-Class Register, Upper Byte
Offset: 0x0B
B its 7:0 F ie l d Ty p e / I n it Va l RO Function 0: 0x05 Function 1: 0x08 Function 2: 0x04 D e s c r ip t i o n Broadly classifies the functions of the adapter Fixed Value = 0x05 for Function0 (NAND Flash) Fixed Value = 0x08 for Function1 (SD) Fixed Value = 0x04 for Function2 (Camera)
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88ALP01 Datasheet
3.2.2.7
Cache Line Register
The Cache Line Register comprises 8 bits. The register is reloadable from the VPD serial EEPROM (not recommended).
Table 35: Cache Line Size Register
Offset: 0x0C
B its 7:0 F ie l d Cache line size Ty p e / I n it Va l RW 0 D e s c r i p t io n Specifies the system cache line in units of 32-bit words. The adapter supports cache line sizes of 4, 8, 16, 32, 64 or 128 dwords. Setting this register to 1, 2, or 3 is treated like being set to 0. The Cache Line Size is restricted to be a power of two. The most significant 1 in this register is used to set the Cache Line Size. Any other 1's are ignored. The adapter as bus master uses this field as criteria for starting transfers from/to complete cache lines with the Memory Write and Invalidate, Read Line, and Read Multiple commands. It also uses it to determine the disconnection of burst accesses at cache line boundaries.
3.2.2.8
Latency Timer Register
The Latency Timer Register comprises 8 bits and is reloadable from the VPD serial EEPROM (not recommended).
Table 36: Latency Timer Register
Offset: 0x0D
B its 7:0 F ie l d Latency Timer Ty p e / I n it Va l RW 0 D e s c r i p t io n Specifies the maximum time the adapter can continue with bus master transfers after the system arbiter has removed GNTn. The time is specified in units of PCI bus clocks. The working copy of the Timer starts counting down when the adapter asserts FRAMEn for the first time during a bus mastership period. The Timer freezes at ZERO. When the Timer is ZERO and GNTn is deasserted by the system arbiter, the adapter finishes the current data phase and then immediately releases the bus.
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Register Description
PCI Configuration Register File
3.2.2.9
Header Type Register
The header type register comprises 8 bits. This register describes the format of the PCI configuration space locations 0x10 to 0x3c and states whether the PCI device is a single function or multi function device.
Table 37: Base-Class Register
Offset: 0x0E
B its 7 6:0 F ie l d Ty p e / I n it Va l RO 1 RO 0 D e s c r i p t io n Single function/multi function device Fixed value = 1, the adapter is a multi function device. PCI configuration space layout Fixed value = 0, the layout of the PCI configuration space locations 0x10 to 0x3c is as shown in the table above.
3.2.2.10
Built-in Self Test Register
The optional Built-in Self Test Register comprises 8 bits.
Table 38: Built-in Self Test Register
Offset: 0x0F
B its 7:0 F ie l d Built-in Self Test Ty p e / I n it Va l RO 0 D e s c r i p t io n BIST is not supported (optional) Fixed value = 0
3.2.2.11
Base Address Register (1st)
The 1st Base Address Register is a 32-bit register that determines the location of the adapter in the memory space, if memory mapping is used. The base address register is reloadable from the VPD serial EEPROM.
Table 39: Base Address Register (1st)
Offset: 0x10
B its 31:14 13:4 F ie l d Ty p e / I n it Va l D e s c r i p t io n Lower 18 bits of most significant bits of memory base address. Memory size requirements Fixed value, indicates memory space requirement of 16384 bytes. Prefetch Enable Fixed value, indicates that prefetching is not allowed.
Lower MEMBASE RW 0 MEMSIZE RO 0 RO 0
3
PREFEN
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88ALP01 Datasheet
Table 39: Base Address Register (1st) (Continued)
Offset: 0x10
B its 2:1 F ie l d Memory Type Ty p e / I n it Va l RO 0x0 D e s c r i p t io n Memory Type 00 = Base register is 32 bits wide, and mapping can be done anywhere in the 32-bit memory space. 10 = Base register is 64 bits wide and can be mapped anywhere in the 64-bit address space. Memory Type may be reloaded out of the VPD TWSI EEPROM (further memory types). NOTE: PCI Specification Rev. 2.2 does not allow mappings below 1MB. Memory Space Indicator Fixed value, indicates that this Base Address Register describes a memory base address.
0
MEMSPACE
RO 0
3.2.2.12
Subsystem Vendor ID Register
The Subsystem Vendor ID Register comprises 16 bits and can be used for customizing OEM versions. The unique vendor ID of the OEM allocated by the PCI SIG may be provided here. It is reloadable from the VPD serial EEPROM.
Table 40: Subsystem Vendor ID Register
Offset: 0x2C
B its 15:0 F ie l d Subsystem Vendor ID Ty p e / I n it Va l RO 0x11AB D e s c r i p t io n Identifies the subsystem vendor ID. Must be a valid non-zero value.
3.2.2.13
Subsystem ID Register
The Subsystem ID Register comprises 16 bits and can be used for customizing OEM versions. It is reloadable from the VPD serial EEPROM.
Table 41: Subsystem ID Register
Offset: 0x2E
B its 15:0 F ie l d Subsystem ID Ty p e / I n it Va l RO 0x4100 D e s c r i p t io n Identifies the subsystem. Must be a valid non-zero value.
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Register Description
PCI Configuration Register File
3.2.2.14
New Capabilities Pointer
The New Capabilities Pointer Register comprises 8 bits that points to the New Capabilities List. This pointer register is reloadable from the VPD serial EEPROM.
Table 42: New Capabilities Pointer Register
Offset: 0x34
B its 7:0 F ie l d New Capabilities Pointer Ty p e / I n it Va l RO 0x88 D e s c r i p t io n Points to the New Capabilities List
3.2.2.15
Interrupt Line Register
The Interrupt Line Register comprises 8 bits.
Table 43: Interrupt Line Register
Offset: 0x3C
B its 7:0 F ie l d Ty p e / I n it Va l RW 0 D e s c r i p t io n The Interrupt Line Register is used to communicate interrupt line routing information. POST software writes the routing information into this register as it initializes and configures the system. The value in this register indicates, to which input of the system interrupt controller(s) the devices's interrupt pin is connected. Device drivers and operating systems can use this information to determine priority and vector information. The Interrupt Line Register is not modified by the adapter. It has no effect on the operation of the device.
3.2.2.16
Interrupt Pin Register
The Interrupt Pin Register comprises 8 bits.
Table 44: Interrupt Pin Register
Offset: 0x3D
B its 7:0 F ie l d Interrupt Pin Ty p e / I n it Va l RO 0x01 D e s c r i p t io n Fixed value, the adapter uses the interrupt pin INTAn.
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88ALP01 Datasheet
3.2.2.17
Min_Gnt Register
The Minimum Grant Time (Min_GNT) Register comprises 8 bits. It is reloadable from the VPD serial EEPROM.
Table 45: Min_Gnt Register
Offset: 0x3E
B its 7:0 F ie l d Min_Gnt Ty p e / I n it Va l RO 0x08 D e s c r i p t io n This read-only register specifies the adapter's desired settings for Latency Timer Value. The value specifies, in units of 1/4 microseconds, the burst period needed by the adapter assuming a clock rate of 33 MHz.
3.2.2.18
Max_Lat Register
The Maximum Latency (Max_Lat) Register comprises 8 bits and is reloadable from the VPD serial EEPROM.
Table 46: Max_Lat Register
Offset: 0x3F
B its 7:0 F ie l d Max_Lat Ty p e / I n it Va l RO 0x08 D e s c r i p t io n This read-only register specifies the adapter's desired settings for Latency Timer Value. The value specifies, in units of 1/4 microseconds, how often the adapter needs to gain access to the PCI bus assuming a clock rate of 33 MHz.
3.2.2.19
Expansion ROM Base Address Register
Expansion ROM is not supported, this location is treated like reserved locations.
3.2.3
Device Dependent Region
Control Access Register and VPD Control Register are the first two used locations in the "device dependent region" of the 256-byte configuration space. The default values are chosen for the most common environments. Modifications may be handled as manufacturing option, driver options, or dedicated configuration software.
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Register Description
PCI Configuration Register File
3.2.3.1
SD Slot Information Register
The SD Slot Information Register is only used for function 1.
Table 47: SD Slot Information Register
Offset: 0x40
B its 7 6:4 F ie l d Reserved Number of Slots Ty p e / I n it Va l RSVD RO 0x0 D e s c r i p t io n Reserved for future use Number of Slots These statuses indicate the number of slots the Host Controller supports. 000 = 1 slot All other values are reserved. Reserved for future use First Base Address Register Number These bits indicate the first Base Address register number assigned for the SD Host Controller register set. 000 = Base address 0x10 (BAR0) All other values are reserved.
3 2:0
Reserved
RSVD
RO First Base Address Register 0x0 Number
3.2.3.2
Access Control and VPD Control Registers
Control Access Register and VPD Control Register are 32-bit registers. Both are reloadable from the VPD serial EEPROM. Most of the switches in Access Control and VPD Control are not intended for use at run time. Manufactured adapters may come up with different settings than defined as Reset Value (if reloaded from the VPD serial EEPROM). The fields marked with "RO" in column "Write" are writable only in test mode. The fields marked with "RW" are writable in configuration space and with normal accesses to the Control Register File.
Table 48: Access Control Register
Offset: 0x80
B its 31 30 29:24 23 F ie l d Reserved DLL_DIS Reserved En IO Mapping Ty p e / I n it Va l RSVD RW 0x0 RSVD RO 0x0 D e s c r i p t io n Reserved for future use Disable DLL Reserved for future use Controls mapping of the Control Register File to the I/O space (manufacturing option). 1 = Address decoding for I/O accesses enabled 0 = Any address decoding for I/O accesses is disabled Reserved for future use
22:14
Reserved
RSVD
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88ALP01 Datasheet
Table 48: Access Control Register (Continued)
Offset: 0x80
B its 13 F ie l d Dis MRL Ty p e / I n it Va l RW 0x0 RW 0x0 RW 0x0 RSVD RW 0x0 RW 0x0 RW 0x0 D e s c r i p t io n Conventional PCI: 1 = Disable command Memory Read Line 0 = Enable command Memory Read Line Conventional PCI: 1 = Disable command Memory Read Multiple 0 = Enable command Memory Read Multiple Conventional PCI: 1 = Disable Command Memory Write and Invalidate 0 = Enable command Memory Write and Invalidate Reserved for future use Conventional PCI: 1 = Enables BIU master "read 1.5" feature Conventional PCI: 1 = Write combining is enabled Conventional PCI: 1 = Read combining is enabled
12
Dis MRM
11
Dis MWI
10:3 2 1 0
Reserved En Rd15 En Wr Comb En Rd Comb
Table 49: VPD Control Register
Offset: 0x84
NOTE: This register is only applicable to function 0 (NAND Flash Controller). B its 31:24 23:17 F ie l d Reserved_RW VPD Devsel RO 0x50 Defines the Device Select Byte for the serial EEPROM used for VPD storage. Default value is 0b1010000. NOTE: VPD Devsel must not be overwritten via serial EEPROM! This may lead to a complete damage of the board (Serial EEPROM must be changed afterwards)! Defines the size of the assembled serial EEPROM in Bytes. 0x0 = 256 Bytes 0x1 = 512 Bytes 0x2 = 1024 Bytes 0x3 = 2048 Bytes 0x4 = 4096 Bytes 0x5 = 8192 Bytes 0x6 = 16384 Bytes 0x7 = 32768 Bytes Default value is 2048 Bytes. If any other size is used, this field must be reprogrammed out of the SPI Flash Memory. Due to currently used addressing procedure via TWSI bus only applications up to size 2048 Bytes are supported. Ty p e / I n it Va l D e s c r i p t io n
16:14
VPD ROM Size
RO 0x3
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Register Description
PCI Configuration Register File
Table 49: VPD Control Register (Continued)
Offset: 0x84
NOTE: This register is only applicable to function 0 (NAND Flash Controller). B its 13:0 F ie l d Reserved Ty p e / I n it Va l RSVD D e s c r i p t io n Reserved for future use
3.2.3.3
Power Management Capability ID Register
The Power Management Capability ID comprises 8 bits. Power Management is the first "New Capability" in the New Capabilities list. The New Capabilities pointer at address 0x34 contains the address 0x48 for the first entry in the New Capabilities list. The Next Item Pointer at address 0x49 holds the address of the next entry in the New Capabilities list. For 88ALP01 this is the Vital Product Data VPD New Capability ID. The attached Next Item Pointer holds a 0x0 in 88ALP01 indicating the end of the New Capabilities list. The New Capabilities linked list uses New Capability IDs for the unique identification of the capability. New Capability IDs are assigned by the PCI SIG. The structure of New Capability information is also specified by the PCI SIG, e.g. Power Management has a New Capability ID of 0x01. The structure of the related information is specified in the PCI Power Management Interface Specification. The ID for VPD is 0x03. The structure of New Capability information is defined in the PCI Specification Rev. 2.2. The Power Management New Capability ID Register is reloadable from the VPD serial EEPROM.
Table 50: Power Management Capability ID Register
Offset: 0x88
B its 7:0 F ie l d Cap ID Ty p e / I n it Va l RO 0x01 D e s c r i p t io n Power Management Capabilities ID
3.2.3.4
Power Management Next Item Pointer
The Power Management Next Item Pointer comprises 8 bits. It is reloadable from the VPD serial EEPROM.
Table 51: Power Management Next Item Pointer
Offset: 0x89
B its 7:0 F ie l d Next Item Ptr Ty p e / I n it Va l RO 0x9C D e s c r i p t io n Pointer to the Next Item in the capabilities list
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88ALP01 Datasheet
3.2.3.5
Power Management Capabilities Register
The Power Management Capabilities Register comprises 16 bits. It is reloadable from the VPD serial EEPROM.
Table 52: Power Management Capabilities Register
Offset: 0x8A
B its 15 F ie l d PME Support Ty p e / I n it Va l RO 0 (0 if no Vaux) D e s c r ip t i o n Power Management Event Support: Specifies power state in which the signal PMEn may be asserted. If no VAUX is available, this bit is forced to ZERO, signalling no PMEn support in D3cold. 1 = PMEn can be asserted from D3cold, if Vaux is available 0 = PMEn cannot be asserted from D3cold, if Vaux is not available
14
Power Management Event Support: Specifies power RO Function 0 and 2: 0 state in which the signal PMEn may be asserted. 1 = PMEn can be asserted from D3hot Function 1: 1 Power Management Event Support: Specifies power RO Function 0 and 2: 0 state in which the signal PMEn may be asserted. 1 = PMEn can be asserted from D2 Function 1: 1 RO 0 Power Management Event Support: Specifies power state in which the signal PMEn may be asserted. 1 = PMEn can be asserted from D1
13
12
11
RO Power Management Event Support: Specifies power Function 0 and 2: 0 state in which the signal PMEn may be asserted. Function 1: 1 1 = PMEn can be asserted from D0 D2 Support RO D2 Support Function 0 and 2: 0 0 = The adapter does not support D2 Power Function 1: 1 Management State. 1 = The adapter supports D2 Power Management State. RO D1 Support Function 0 and 2: 0 0 = The adapter does not support D1 Power Function 1: 1 Management State. 1 = The adapter supports D1 Power Management State. RO 0b000 RO 0 Reserved, but reloadable from the VPD serial EEPROM for changes in the PCI Specification. Device Specific Initialization: 1 = The adapter requires device specific initialization. 0 = The adapter does not require device specific initialization. Reserved for future use Power Management Event Clock: The adapter does not need PCI Clock for PMEn generation.
10
9
D1 Support
8:6 5
Reserved DSI
4 3
Reserved PME Clock
RSVD RO 0
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Register Description
PCI Configuration Register File
Table 52: Power Management Capabilities Register (Continued)
Offset: 0x8A
B its 2:0 F ie l d Version Ty p e / I n it Va l RO 0x02 D e s c r ip t i o n The adapter complies with Revision 1.1 of the PCI Power Management Interface Specification.
3.2.3.6
Power Management Control/Status Register
The Power Management Control/Status Register comprises 16 bits and is reloadable from the VPD serial EEPROM.
Table 53: Power Management Control/Status Register
Offset: 0x8C
B its 15 14:13 F ie l d PME Status Data Scale Ty p e / I n it Va l SH 0 RO 0b01 RW 0 RW 0 RSVD RW 0 D e s c r i p t io n Indicates that PMEn has been asserted by the adapter. Reset by Power on reset and when written with 1. Indicates the scaling factor to be used when interpreting the value of the Data Register. The read value depends on the setting of the Data Select field. This 4-bit field is used to select which data is to be reported through the Data Register and Data Scale field. Enables PMEn generation. Reset by Power on reset. Reserved for future use Controls the Power Management State of the adapter. The adapter supports all power management states.
12:9 8 7:2 1:0
Data Select PME En Reserved Power State
The 16 2-bit Data_Scale fields and the 16 8-bit Data Register values that can be selected by the Data_Select field, are reloadable from the VPD serial EEPROM by writing complete 32-bit wide sets of Data Select, Data Scale, and Data to the Power Management Control/Status and Data Register.
Caution
To modify the contents of any Data Scale or Data field, the Data Select field MUST always be written with the desired Data Select value in the same 32-bit access!
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88ALP01 Datasheet
3.2.3.7
Power Management Data Register
The Power Management Data Register comprises 8 bits and is reloadable from the VPD serial EEPROM.
Table 54: Power Management Data Register
Offset: 0x8F
B its 7:0 Name Data Ty p e / I n it Va l RO See Table 55 D e s c r i p t io n This read-only register is used to report the state dependent data requested by the Data Select field. The value of this register is scaled by the value reported by the Data Scale field.
3.2.3.8
Power Management Data Table
Data and Data Scale are hidden registers accessible through the Power Management Control/Status Register selected by Data Select. Data Scale is writable from the VPD serial EEPROM loader by writing to Power Management Control/Status Register. Data is writable from the VPD serial EEPROM loader by writing to Power Management Data Register. Data and Data Scale are reloaded from the VPD serial EEPROM with values matching the manufacturing option.
Table 55: Power Management Data Table
Va lu e i n D a ta S el e c t 0 1 2 3 4 5 6 7 8 D3 Power dissipated Common logic power consumption Reserved 0x3 0x1 0x1 0x1 0.3 0.1 D3 Power consumed D0 Power dissipated Reserved 0x3 0x3 0x1 0x1 0.3 0.3 M e an i ng D a ta ( 8 b it ) R e s e t Va lu e 0x3 D a ta S c a l e (2 bit) Reset Va l u e 0x1 [Wa tt ] w it h R es e t Va l u e s 0.3
D0 Power consumed Reserved
9:15
0x0
0x0
0x0
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Register Description
PCI Configuration Register File
3.2.3.9
VPD Capability ID Register
The VPD Capability ID Register comprises 8 bits and is reloadable from the VPD serial EEPROM. It contains the New Capability ID for VPD as specified by the PCI SIG. By default, the VPD capability is turned off. To enable this capability, the default value of the Power Management Next Item Pointer (Table 51 p. 71) must be changed from 0x5C to 0x50 through the initial loading from serial EEPROM.
Table 56: VPD Capability ID Register
Offset: 0x90
NOTE: This register is only applicable to function 0 (NAND Flash Controller). B its 7:0 F ie l d Cap ID Ty p e / I n it Va l RO 0x03 D e s c r i p t io n VPD Capabilities ID
3.2.3.10
VPD Next Item Pointer
The VPD Next Item Pointer comprises 8 bits is reloadable from the VPD serial EEPROM.
Table 57: VPD Next Item Pointer
Offset: 0x91
NOTE: This register is only applicable to function 0 (NAND Flash Controller). B its 7:0 F ie l d Next Item Ptr Ty p e / I n it Va l RO 0x9C D e s c r i p t io n Pointer to the next item in the capabilities list.
3.2.3.11
VPD Address Register
The VPD Address & Data Registers control a TWSI, which runs a 100 kHz protocol to an external TWSI EEPROM. The interface signals are routed through the pins VPD_CLK and VPD_DATA. The TWSI clock and data port pins are pulled high by a pull up resistor to VDDO of the TWSI device. The VPD Address Register comprises 16 bits and is reloadable from the VPD serial EEPROM and is also writable in I/O space.
Table 58: VPD Address Register
Offset: 0x92
NOTE: This register is only applicable to function 0 (NAND Flash Controller). B its 15 F ie l d Flag Ty p e / I n it Va l EXEC 0 D e s c r i p t io n Starts the VPD transfers, determines its direction, and signals its completion by being toggled by HW. If written 1, a VPD write is started. Set to 0 after completion. If written 0, a VPD read is started. Set to 1 after completion. Address of the VPD contents to be written / read.
14:0
VPD Address
RW 0x00
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88ALP01 Datasheet
3.2.3.12
VPD Data Register
The VPD Data Register comprises 32 bits and is reloadable from the VPD serial EEPROM and is also writable in I/O space.
Table 59: VPD Data Registers
Offset: 0x94
NOTE: This register is only applicable to function 0 (NAND Flash Controller). B its 31:0 F ie l d VPD Data Ty p e / I n it Va l RW 0x00 D e s c r i p t io n Must be written before VPD Address Register for VPD Write. Contains VPD Read Data after completion of VPD Read.
3.2.3.13
VPD Serial EEPROM Loader Control Register
The VPD Serial EEPROM Control Register comprises 16 bits and controls the VPD serial EEPROM Loader. It can be written in test mode.
Table 60: VPD Serial EEPROM Loader Control Register
Offset: 0x9A
NOTE: This register is only applicable to function 0 (NAND Flash Controller). B its 15 F ie l d Flag Ty p e / I n it Va l RO 0 RO 0x200 D e s c r i p t io n Starts and stops the data transfer. If written 1, the Serial EEPROM Loader is started. If written 0, the Serial EEPROM Loader is stopped. Start address for Serial EEPROM Loader. Should be min. 256 and in 8 byte steps.
14:0
Serial EEPROM Address
3.2.3.14
MSI Capability ID Register (MSI Cap ID)
The 88ALP01 is capable of Message Signaled Interrupt (MSI) handling. Reloadable out of the VPD TWSI EEPROM.
Table 61: MSI Capability ID Register (MSI Cap ID)
Offset: 0x9C
NOTE: This register is only applicable to function 0 (NAND Flash Controller). B its 7:0 F ie l d Cap ID Ty p e / I n it Va l RO 0x05 D e s c r i p t io n MSI Capabilities ID
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Register Description
PCI Configuration Register File
3.2.3.15
MSI Next Item Pointer
Reloadable out of the VPD TWSI EEPROM.
Table 62: MSI Next Item Pointer Register
Offset: 0x9D
B its 7:0 F ie l d Next Item Ptr Ty p e / I n it Va l RO 0x0 D e s c r i p t io n Pointer to the next item in the capabilities list.
3.2.3.16
MSI Message Control
Reloadable out of the VPD TWSI EEPROM.
Table 63: MSI Message Control Register
Offset: 0x9E
B its 15:8 7 F ie l d Reserved 64 Bit Addr capable Ty p e / I n it Va l RO 0x0 RO 0x1 D e s c r i p t io n Reserved for future use 1 = The device is capable of generating a 64-bit message address 0 = The device is not capable of generating a 64-bit message address Defines the number of allocated messages 0b000 = 1 0b001 = 2 (not supported) 0b010 = 4 (not supported) 0b011 = 8 (not supported) 0b100 = 16 (not supported 0b101 = 32 (not supported) 0b110 = Reserved 0b111 = Reserved This implementation supports one allocated message. 3:1 Multiple Message RO Capable 0x0 System software reads this field to determine the number of requested messages. 0b000 = 1 0b001 = 2 (not supported) 0b010 = 4 (not supported) 0b011 = 8 (not supported) 0b100 = 16 (not supported) 0b101 = 32 (not supported) 0b110 = Reserved 0b111 = Reserved There is one requested message.
6:4
Multiple Message RW Enable 0x0
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88ALP01 Datasheet
Table 63: MSI Message Control Register (Continued)
Offset: 0x9E
B its 0 F ie l d MSI Enable Ty p e / I n it Va l RW 0x0 D e s c r i p t io n 1 = MSI is used to request service. INTAn is disabled. 0 = INTAn is used to request service. MSI is disabled Reset by D3 to D0 reset.
3.2.3.17
MSI Message Address
Reloadable out of the VPD TWSI EEPROM.
Table 64: MSI Message Lower Address Register
Offset: 0xA0
B its 31:2 F ie l d MSI Message Lower Address Ty p e / I n it Va l RW 0x00 D e s c r i p t io n System-specified message address If the field in the MSI Message Control Register (Table 63 p. 78) is set, the contents of this register specify the DWORD aligned address for the MSI memory write transaction. Reserved for future use
1:0
Reserved
RSVD
Table 65: MSI Message Upper Address Register
Offset: 0xA4
B its 31:0 F ie l d MSI Message Upper Address Ty p e / I n it Va l RW 0x00 D e s c r i p t io n System-specified message upper address If the field in the MSI Message Control Register (Table 63 p. 78) is set, the contents of this register (if non-zero) specify the upper 32-bits of a 64-bit message address (AD[63:32]). If the contents of this register are zero, the device uses the 32 bit address specified by the MSI Message Lower Address Register (Table 64 p. 78).
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Register Description
PCI Configuration Register File
3.2.3.18
MSI Message Data
Reloadable out of the VPD TWSI EEPROM.
Table 66: MSI Message Data Register
Offset: 0xA8
B its 31:16 15:0 F ie l d Reserved Message Data Ty p e / I n it Va l RSVD RW 0x00 D e s c r i p t io n Reserved for future use System-specified message If the field in the MSI Message Control Register (Table 63 p. 78) is set, the Message Data is driven onto the lower word (AD[15:00]) of the memory write transaction's data phase. The field in the MSI Message Control Register (Table 63 p. 77) defines the number (only one message supported by the chip).
3.2.3.19
Calibration Control Register
Reloadable out of the TWSI EEPROM.
Table 67: Calibration Control Register
Offset: 0xB4
B its 15:10 9 8 F ie l d Reserved Cal Test Cal En Ty p e / I n it Va l RSVD RO 0x0 RO 0x1 RO 0x0 RO 0x0 D e s c r i p t io n Reserved for future use 1 = Force PCI buffer strength calibration to the maximum value 1 = Enable PCI buffer strength calibration 0 = Force PCI buffer strength according to the calibration control register Force value/p transistors Force value/n transistors
7:4 3:0
Cal P[3:0] Cal N[3:0]
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88ALP01 Datasheet
3.2.3.20
Calibration Status Register
Reloadable out of the TWSI EEPROM.
Table 68: Calibration Status Register
Offset: 0xB6
B its 15:8 7:4 3:0 F ie l d Reserved CalP[3:0] Cal N[3:0] Ty p e / I n it Va l RSVD RO RO D e s c r i p t io n Reserved for future use Calibration result (number of p-channel fingers) Calibration result (number of n-channel fingers)
3.2.3.21
Discard Counter Register
Reloadable out of the TWSI EEPROM.
Table 69: Discard Counter Register
Offset: 0xB8
B its 15:0 F ie l d Dis Cnt Ty p e / I n it Va l RW 0x0000 D e s c r i p t io n Discard Counter Conventional PCI: Number of cycles BIU target waits for transaction retry before giving up and discarding the read data. 0x0000 = Discard Counter is not activated
3.2.3.22
Retry Counter Register
Table 70: Retry Counter Register
Offset: 0xBA
B its 7:0 F ie l d Retry Cnt Ty p e / I n it Va l RW 0x00 D e s c r i p t io n Retry counter Number of times BIU master (also target in case of PCI-X) retries a transaction before giving up. 0 = Retry forever
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Register Description
Global Control Registers
3.3
3.3.1
Global Control Registers
These registers can be accessed from all three functions.
Register Map
Table 71: Global Control Register Map
R e g is t e r N a m e Reserved Control/Status Register Interrupt Source Register Interrupt Mask Register Interrupt HW Error Source Register Interrupt HW Error Mask Register Reserved PLL Control Register Block Control Register GPIO Functional Control Register Reserved Test Control Register General Purpose I/O Register VPD TWSI (HW) Control Register VPD TWSI (HW) Data Register VPD TWSI (HW) IRQ Register VPD TWSI (SW) Register Offset 0x3000 0x3004 0x3008 0x300C 0x3010 0x3014 0x3018 to 0x302C 0x3030 0x3034 0x3038 0x303C to 0x3154 0x3158 0x315C 0x3160 0x3164 0x3168 0x316C Ta b l e a n d P a ge -Table 72, p. 81 Table 73, p. 83 Table 74, p. 83 Table 75, p. 84 Table 76, p. 85 -Table 77, p. 85 Table 78, p. 86 Table 79, p. 86 -Table 80, p. 87 Table 81, p. 87 Table 82, p. 88 Table 83, p. 89 Table 84, p. 89 Table 85, p. 90
3.3.2
3.3.2.1
Register Descriptions
Control/Status
Table 72: Control/Status Register
Offset: 0x3004
B its Status 23:16 Reserved RSVD Reserved for future use F ie l d Ty p e / I n it Va l D e s c r i p t io n
Commands 15 Reserved RSVD Reserved for future use
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88ALP01 Datasheet
Table 72: Control/Status Register (Continued)
Offset: 0x3004
B its 14 F ie l d CCIC Clock Enable Ty p e / I n it Va l RW 0x1 D e s c r i p t io n CCIC Module Clock Enable This bit is only writable from function 2 (CMOS Camera Interface Controller). 0 = Clock is disabled 1 = Clock is enabled SDH Module Clock Enable This bit is only writable from function 1 (SD/SDIO). 0 = Clock is disabled 1 = Clock is enabled NAND Controller Module Clock Enable This bit is only writable from function 0 (NAND Flash Controller). 0 = Clock is disabled 1 = Clock is enabled Sets and clears ClkRunEnable
13
SDH Clock Enable
RW 0x1
12
NAND Clock Enable
RW 0x1
11 10 9:8 7 6 5
ClkRun Enable Set ClkRun Enable Clear Reserved Set IRQ SW Clear IRQ SW
EXEC 0 EXEC 1 RSVD EXEC 0 EXEC 1
Reserved for future use Sets and clears Interrupt Request from SW
Stop Master Done RO 0 Stop Master RW 0 (HW)
As soon as the Master Statemachine is in the idle state after Stop Master is set, Stop Master Done is asserted. Stop Master Done is reset to 0 by resetting Stop Master. If Stop Master is set, all requests from the BMUs except for the one being serviced at the moment, are masked. The Master Statemachine reaches the idle state after the current request is serviced. Stop Master has to be reset by the SW after the BMUs are reset. If the BMUs are not reset, the 88ALP01 resumes master action at the point when it was interrupted by Stop Master. Set/Clear Master Reset If Master Reset is set, all devices related to the master interface (BMUs, FIFOs, State machines) are in their reset state. Executed, if appropriate bit is set to 1. Set/Clear SW Reset Executed if appropriate bit is set to 1. If SW Reset is set, all internal and external devices are in their reset state.
4
3 2
Master Reset Clear
EXEC 1
Master Reset Set EXEC 0 (SW) SW Reset Clear SW Reset Set EXEC 1 EXEC 0 (HW)
1 0
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Register Description
Global Control Registers
3.3.2.2
Interrupt Source Register
Table 73: Interrupt Source Register
Offset: 0x3008
B its 31 F ie l d PCI Error Interrupt Ty p e / I n it Va l RO 0x0 D e s c r i p t io n PCI Error Interrupt 1 = At least one of the HW Interrupts occurred (Interrupt HW Error Source Register (Table 75 p. 84)) 0 = No HW interrupt active Reserved for future use Interrupt on completion of VPD TWSI transfer 0 = Interrupt is not pending 1 = Interrupt is pending Reserved for future use CCIC Interrupt 0 = Interrupt is not pending 1 = Interrupt is pending SDIO Interrupt 0 = Interrupt is not pending 1 = Interrupt is pending NAND Flash Interrupt 0 = Interrupt is not pending 1 = Interrupt is pending
30:27 26
Reserved IRQ VPD TWSI Ready Reserved IRQ CCIC
RSVD RO 0x0 RSVD RO 0x0 RO 0x0 RO 0x0
25:3 2
1
IRQ SDH
0
IRQ NAND
3.3.2.3
Interrupt Mask Register
Each bit position defines, if the dedicated interrupt is propagated to the internal interrupt line irq. The enable bits have the same bit positions as in the Interrupt Source Register (Table 73 p. 83). Unused bit positions are treated like reserved.
Table 74: Interrupt Mask Register
Offset: 0x300C
B its 31 F ie l d En IRQ HW Interrupt Reserved En IRQ VPD TWSI Ready Reserved Ty p e / I n it Va l RW 0 (SW) RSVD RO 0x0 RSVD D e s c r i p t io n Enable Interrupt HW Interrupt 0 = Interrupt disabled 1 = Interrupt enabled Reserved for future use Enable Interrupt on Completion of VPD TWSI Transfer 0 = Interrupt disabled 1 = Interrupt enabled Reserved for future use
30:27 26
25:3
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88ALP01 Datasheet
Table 74: Interrupt Mask Register (Continued)
Offset: 0x300C
B its 2 F ie l d En IRQ CCIC Ty p e / I n it Va l RW 0 (SW) D e s c r i p t io n Enable CCIC Interrupt This bit is only writable from function 2 (CMOS Camera Interface Controller). 0 = Interrupt disabled 1 = Interrupt enabled Enable SDIO Interrupt This bit is only writable from function 1 (SD/SDIO). 0 = Interrupt disabled 1 = Interrupt enabled Enable NAND Flash Interrupt This bit is only writable from function 0 (NAND Flash Controller). 0 = Interrupt disabled 1 = Interrupt enabled
1
En IRQ SDH
RW 0 (SW)
0
En IRQ NAND
RW 0 (SW)
3.3.2.4
Interrupt HW Error Source Register
Table 75: Interrupt HW Error Source Register
Offset: 0x3010
B its F ie l d Ty p e / I n it Va l D e s c r i p t io n
General Interrupts 31:28 27 Reserved RSVD Reserved for future use Interrupt Master Error detected on master accesses Set if , , or are set in the Status Register (Table 30 p. 62). Interrupt Status Exception Set if , , , or are set in the Status Register (Table 30 p. 62). Reserved for future use
IRQ Master Error RO 0 (SW) IRQ Status RO 0 (SW)
26
25:0
Reserved
RSVD
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Register Description
Global Control Registers
3.3.2.5
Interrupt HW Error Mask Register
Each bit position defines if the dedicated interrupt is propagated to the Interrupt Line INTAn. The enable bits have the same bit positions as in the Interrupt HW Error Source Register (Table 75 p. 84). Unused bit positions are treated like reserved.
Table 76: Interrupt HW Error Mask Register
Offset: 0x3014
B its F ie l d Ty p e / I n it Va l D e s c r i p t io n
General Interrupts 31:28 27 Reserved En IRQ Master Error RSVD RW 0 (SW) Reserved for future use Enable Interrupt Master Error Detected on Master Accesses 0 = Interrupt disabled 1 = Interrupt enabled Enable Interrupt Status Exception 0 = Interrupt disabled 1 = Interrupt enabled Reserved for future use
26
En IRQ Status
RW 0 (SW) RSVD
25:0
Reserved
3.3.2.6
PLL Control Register
Table 77: PLL Control Register
Offset: 0x3030
B its 31:20 19:17 16 F ie l d Reserved ICHP DIS_PLL_CLK Ty p e / I n it Va l RSVD RW 0x0 RW 0 RW 0x3E RW 0x6 D e s c r i p t io n Reserved for future use PLL ICHP Value Disable PLL Clock Output 0 = Enabled 1 = Disabled PLL N Value PLL M Value
15:8 7:0
PLL_N PLL_M
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88ALP01 Datasheet
3.3.2.7
Block Control Register
Table 78: Block Control Register
Offset: 0x3034
B its 31:3 2 F ie l d Reserved CCIC Soft Reset Ty p e / I n it Va l RSVD RW 0x0 D e s c r i p t io n Reserved for future use CCIC Soft Reset This bit is only writable from function 2 (CMOS Camera Interface Controller). 0 = CCIC block not in reset 1 = CCIC block in reset SDIO Soft Reset This bit is only writable from function 1 (SD/SDIO). 0 = SDH block not in reset 1 = SDH block in reset NAND Flash Soft Reset This bit is only writable from function 0 (NAND Flash Controller). 0 = NFU block not in reset 1 = NFU block in reset
1
SDH Soft Reset
RW 0x0
0
NFU Soft Reset
RW 0x0
3.3.2.8
GPIO Functional Control Register
Table 79: GPIO Functional Control Register
Offset: 0x3038
B its 31:4 3 F ie l d Reserved GPIO Function Control[3] Ty p e / I n it Va l RSVD RW 0x1 D e s c r i p t io n Reserved for future use GPIO Function Control [3] 0 = Functional mode 1 = GPIO mode NOTE: This bit is only accessible from Function 2. GPIO Function Control [2] 0 = Functional mode 1 = GPIO mode NOTE: This bit is only accessible from Function 1. GPIO Function Control [1] 0 = Functional mode 1 = GPIO mode NOTE: This bit is only accessible from Function 1. GPIO Function Control [0] 0 = Functional mode 1 = GPIO mode NOTE: This bit is only accessible from Function 1.
2
GPIO Function Control[2]
RW 0x0
1
GPIO Function Control[1]
RW 0x0
0
GPIO Function Control[0]
RW 0x0
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Register Description
Global Control Registers
3.3.2.9
Test Control Register
Reset by SW Reset.
Table 80: Test Control Register
Offset: 0x3158
B its 7:2 1 0 F ie l d Reserved En Config Write On En Config Write Off Ty p e / I n it Va l RSVD EXEC 0x01 D e s c r i p t io n Reserved for future use Enables write accesses to the Configuration Registers over the Control Register File. The whole VPD TWSI EEPROM is writable when En Config Write is set. Enables write access to some of the write protected Control Registers and the functionality is mentioned explicitly within the description of these registers.
3.3.2.10
General Purpose I/O Register
Table 81: General Purpose I/O Register
Offset: 0x315C
B its 31:20 19 F ie l d Reserved GPIO Dir[3] Ty p e / I n it Va l RSVD RW 0x0 D e s c r i p t io n Reserved for future use GPIO Dir[3] Defines the type of GPIO pins 0 = Input 1 = Output NOTE: This bit is only accessible from Function 2. GPIO Dir[2] Defines the type of GPIO pins 0 = Input 1 = Output NOTE: This bit is only accessible from Function 1. GPIO Dir[1] Defines the type of GPIO pins 0 = Input 1 = Output NOTE: This bit is only accessible from Function 1. GPIO Dir[0] Defines the type of GPIO pins 0 = Input 1 = Output NOTE: This bit is only accessible from Function 1. Reserved for future use These bits are routed to the chip's pins for future external options. NOTE: This bit is only accessible from Function 2.
18
GPIO Dir[2]
RW 0x1
17
GPIO Dir[1]
RW 0x0
16
GPIO Dir[0]
RW 0x1
15:4 3
Reserved GPIO[3]
RSVD RW 0x0
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88ALP01 Datasheet
Table 81: General Purpose I/O Register (Continued)
Offset: 0x315C
B its 2 F ie l d GPIO[2] Ty p e / I n it Va l RW 0x0 RW 0x0 RW 0x0 D e s c r i p t io n These bits are routed to the chip's pins for future external options. NOTE: This bit is only accessible from Function 1. These bits are routed to the chip's pins for future external options. NOTE: This bit is only accessible from Function 1. These bits are routed to the chip's pins for future external options. NOTE: This bit is only accessible from Function 1.
1
GPIO[1]
0
GPIO[0]
3.3.2.11
VPD TWSI (HW) Registers
These registers implement a serial TWSI to the optional temperature/voltage sensor. Hardware runs the 100 kHz serial TWSI protocol to obtain data.
The hardware controlled TWSI and the software controlled TWSI are connected to the same TWSI bus (pins VPD_DATA and VPD_CLK). They must not be used in parallel. Caution If the hardware controlled TWSI is used, the VPD TWSI (SW) Register (Table 85 p. 90) has to be set to inactive values (Reset values). If the software controlled VPD TWSI is used, the hardware controlled VPD TWSI MUST NOT be started ( field in the VPD TWSI (HW) Control Register (Table 82 p. 88)). The VPD TWSI clock and data port pins are pulled high by a pull up resistor to VDDO of the TWSI device.
Table 82: VPD TWSI (HW) Control Register
Offset: 0x3160
B its 31 F ie l d Flag Ty p e / I n it Va l EXEC 0x0 D e s c r i p t io n Starts the TWSI data transfers, determines its direction and signals its completion by being toggled by hardware. 1 = TWSI write is started and set back to 0 after completion 0 = TWSI read is started and set back to 1 after completion Generates an interrupt upon completion. Address of the TWSI device register to be written/read. Devsel Byte of the TWSI device to be written/read. Reserved for future use 0 = Single byte transfers 1 = 7 byte Page Mode write transfers with fixed page size of 8 bytes assumed
30:16 15:9 8:5 4
TWSI Address TWSI Devsel Reserved TWSI Burst
RW 0x00 RW 0x00 RSVD RW 0x0
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Register Description
Global Control Registers
Table 82: VPD TWSI (HW) Control Register (Continued)
Offset: 0x3160
B its 3:1 F ie l d VPD TWSI Device Size Ty p e / I n it Va l RW 0x00 D e s c r i p t io n Defines the size of the addressed TWSI Device in bytes 0 = 256 bytes and smaller 1 = 512 bytes 2 = 1024 bytes 3 = 2048 bytes 4 = 4096 bytes 5 = 8192 bytes 6 = 16384 bytes 7 = 32768 bytes A written 1 interrupts the current VPD TWSI transfer at the next byte boundary with a stop condition and signals end of TWSI transfer by toggling .
0
TWSI Stop
EXEC 0
Table 83: VPD TWSI (HW) Data Register
Offset: 0x3164
B its 31:0 F ie l d TWSI Data Ty p e / I n it Va l RW 0x00 D e s c r i p t io n Must be written before TWSI Address Register for TWSI write. Contains TWSI read data after completion of TWSI read.
Table 84: VPD TWSI (HW) IRQ Register
Offset: 0x3168
B its 31:1 0 F ie l d Reserved Clear IRQ VPD TWSI Ty p e / I n it Va l RSVD EXEC 0x0 D e s c r i p t io n Reserved for future use Clears Interrupt Request from TWSI hardware interface
3.3.2.12
VPD TWSI (SW) Register
This register implements a serial TWSI to the optional temperature/voltage sensor. SW has to run the serial TWSI protocol to obtain data. As output, the Data Port must simulate an open collector output in order to obtain a 0.7 VDDO signal level at the TWSI device. Driving to low level:
* * * *
TWSI Data = 0 TWSI Data Dir = 1 Floating to high level: TWSI Data = x TWSI Data Dir = 0
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88ALP01 Datasheet
The hardware controlled TWSI and the software controlled TWSI are connected to the same TWSI bus (pins VPD_DATA and VPD_CLK). They must not be used in parallel. Caution If the hardware controlled TWSI is used, the VPD TWSI (SW) Register (Table 85 p. 90) has to be set to inactive values (Reset values). If the software controlled TWSI is used, the hardware controlled TWSI must not be started ( field in the VPD TWSI (HW) Control Register (Table 82 p. 88)). The TWSI clock and data port pins are pulled high by a pull up resistor to VDDO of the TWSI device.
Table 85: VPD TWSI (SW) Register
Offset: 0x316C
B its 31:3 2 F ie l d Reserved TWSI Data Dir Ty p e / I n it Va l RSVD RW 0x0 (SW) RW 0x0 (SW) RW 1 (SW) D e s c r i p t io n Reserved for future use Defines direction of TWSI Data Port: 0 = Input 1 = Output TWSI Data Port TWSI Clock
1 0
TWSI Data TWSI Clock
3.4
3.4.1
NAND Flash Unit
Register Map
Table 86: NAND Flash Unit Registers
R e g is t e r N a m e Control Register Control Register 2 Control Register 3 Status Register Interrupt Register Interrupt Mask Register Data Length Register Address Register Address Register 2 Timing Parameter Register 1 Timing Parameter Register 2 Timing Parameter Register 3 Non-Memory Read Data Register Read ECC Generated Code Register Offset 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 Ta b le a nd Pa g e Table 87, p. 91 Table 88, p. 92 Table 89, p. 93 Table 90, p. 93 Table 91, p. 93 Table 92, p. 94 Table 93, p. 94 Table 94, p. 94 Table 95, p. 95 Table 96, p. 95 Table 97, p. 96 Table 98, p. 96 Table 99, p. 97 Table 100, p. 97
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Register Description
NAND Flash Unit
Table 86: NAND Flash Unit Registers (Continued)
R e g is t e r N a m e Read ECC Read Code Register Read ECC Result Register DMA Control Register DMA Address Register 0 Reserved RS ECC Decode CRC Register RS ECC Decode Syndrome 0 and 1 Register RS ECC Decode Syndrome 2 and 3 Register RS ECC Decode Syndrome 4 and 5 Register RS ECC Decode Syndrome 6 and 7 Register Control Register 4 NAND I/O Drive Strength Register Read Data Registers Reserved Write Data Registers Reserved Offset 0x38 0x3C 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x1000 to 0x183C 0x1840 to 0x1FFC 0x2000 to 0x283C 0x2840 to 0x2FFC Ta b le a nd Pa g e Table 101, p. 97 Table 102, p. 97 Table 103, p. 98 Table 104, p. 98 -Table 105, p. 98 Table 106, p. 99 Table 107, p. 99 Table 108, p. 99 Table 109, p. 100 Table 110, p. 100 Table 111, p. 100 Table 112, p. 100 -Table 113, p. 101 --
3.4.2
Registers
Table 87: Control Register
Offset: 0x00
B its 31 30 29:27 F ie l d cmd_vld do_addr_cyc num_addr_cyc Ty p e / I n it Va l RW 0x0 RW 0x0 RW 0x0 D e s c r i p t io n Command Valid (clear on write) 0 = No operation 1 = Command sequence has address cycle Number of Address Cycle 0b000 = 1 cycle (Default) 0b001 = 2 cycles ... 0b111 = 8 cycles 0 = No operation 1 = Command sequence read data from NAND Flash memory cell 0 = No operation 1 = Command writes data to NAND Flash memory cell These bits are for use in commands such as status read and id read. 0 = Data operation 1 = Number of non-memory cell reads (read ID or read status commands)
26
rd
RW 0x0 RW 0x0
25 24:22
wr
num_nonmem_rd RW [3:1] 0x0
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88ALP01 Datasheet
Table 87: Control Register (Continued)
Offset: 0x00
B its 21 F ie l d Ty p e / I n it Va l D e s c r i p t io n Wait Busy After Sequence After the command sequence is done, the command waits for trp, then returns to idle. 0 = Enabled 1 = Disabled These bits are for use in commands such as status read and id read. 0 = Data operation 1 = Number of non-memory cell reads (read ID or read status commands) 0 = Use CE[0]n 1 = Use CE[1]n Reserved Command This is the value driven on NF_IO[7:0] when NF_CLE is asserted.
wait_bsy_aft_seq RW 0x0
20
num_nonmem_rd RW [0] 0x0
19 18:8 7:0
use_ce_1 Reserved cmd
RW 0x0 RSVD 0x0 RW 0x0
Table 88: Control Register 2
Offset: 0x04
B its 31 30 29:28 F ie l d Reserved Ty p e / I n it Va l RW 0x0 D e s c r i p t io n Reserved for future use 0 = No operation 1 = Automatic generate and write ECC to write buffer Page Size 0b00 = 512 bytes (Default) 0b10 = 2 KBs ECC Select 0 = Hamming code 1 = Reed-Solomon code Reserved for future use 0 = No operation 1 = Second command valid Second Command This is the value driven on NF_IO[7:0] during the second NF_CLE. NOTE: For read operation, the second command comes right after address cycles. For write command, the second command comes after data out cycles.
auto_wr_ecc2bffr RW 0x0 pg_size RW 0x0 RW 0x0 RSVD RW 0x0 RW 0x0
27
ecc_sel
27:9 8 7:0
Reserved cmd2_vld cmd2
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Register Description
NAND Flash Unit
Table 89: Control Register 3
Offset: 0x08
B its 31 F ie l d rd_bsy_rst Ty p e / I n it Va l RW 0x0 RW 0x0 RSVD D e s c r i p t io n Read Busy Reset 1 = Send reset command to NAND device when device rdy==0. 0 = No operation 1 = Write protect bar to NAND device Reserved for future use
30 29:0
wp_val Reserved
Table 90: Status Register
Offset: 0x0C
B its 31 30 29:0 F ie l d nand_dev_bsy nand_dev_rdy Reserved Ty p e / I n it Va l RO 0x0 RO RSVD D e s c r i p t io n 0 = No operation 1 = NAND device is busy 0 = No operation 1 = NAND Flash device is ready Reserved for future use
Table 91: Interrupt Register
Offset: 0x10
B its 31 30 29 28 27 26:0 F ie l d cmd_done flash_rdy Reserved dma_done boot_done Reserved Ty p e / I n it Va l RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RSVD 0x0 D e s c r i p t io n Command Done 1 = Write 1 to clear interrupt Flash is Ready 1 = Write 1 to clear interrupt Reserved for future use DMA Done Interrupt 1 = Write 1 to clear interrupt Auto Boot Load Done Interrupt 1 = Write 1 to clear interrupt Reserved for future use
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88ALP01 Datasheet
Table 92: Interrupt Mask Register
Offset: 0x14
B its 31 F ie l d Ty p e / I n it Va l D e s c r i p t io n Command Done Interrupt Mask 1 = Masked (Default) 0 = Not masked Flash Ready Interrupt Mask 1 = Masked (Default) 0 = Not masked Reserved for future use DMA Done Interrupt Mask 1 = Masked (Default) 0 = Not masked Boot Done Interrupt Mask 1 = Masked (Default) 0 = Not masked Reserved for future use
cmd_done_mask RW 0x1 flash_rdy_mask RW 0x1 RW 0x1
30
29 28
Reserved
dma_done_int_m RW ask 0x1 boot_done_int_m RW ask 0x1 Reserved RSVD 0x1
27
26:0
Table 93: Data Length Register
Offset: 0x18
B its 31:12 11:0 F ie l d Reserved num_bytes Ty p e / I n it Va l RSVD 0x0 RW 0x0 D e s c r i p t io n Reserved for future use Number of Bytes to Read/Write
Table 94: Address Register
Offset: 0x1C
B its 31:16 15:8 F ie l d Reserved addr_1 Ty p e / I n it Va l RSVD 0x0 RW 0x0 RW 0x0 D e s c r i p t io n Reserved for future use Address 1 This is the value driven on NF_IO[7:0] during the second NF_ALE. Address 0 This is the value driven on NF_IO[7:0] during the first NF_ALE.
7:0
addr_0
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Register Description
NAND Flash Unit
Table 95: Address Register 2
Offset: 0x20
B its 31:24 23:16 F ie l d Reserved addr_4 Ty p e / I n it Va l RSVD 0x0 RW 0x0 RW 0x0 RW 0x0 D e s c r i p t io n Reserved for future use Address 4 This is the value driven on NF_IO[7:0] during the fifth NF_ALE. Address 3 This is the value driven on NF_IO[7:0] during the fourth NF_ALE. Address 2 This is the value driven on NF_IO[7:0] during the third NF_ALE.
15:8
addr_3
7:0
addr_2
Table 96: Timing Parameter Register 1
Offset: 0x24
NOTE: The bits in this register are NAND Flash part-dependent timing parameters specified in number of internal NAND Flash clock. For descriptions of these bits, refer to documentation on the NAND Flash part that is being implemented. B its 31:28 27:24 23:20 19:16 15:8 7:0 F ie l d tcls tclh tals talh twb trb Ty p e / I n it Va l RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 D e s c r i p t io n CLE Setup Time CLE Hold Time ALE Setup Time ALE Hold Time WE High to Busy Amount of time needed to wait to validate ready before starting to sample
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Table 97: Timing Parameter Register 2
Offset: 0x28
NOTE: The bits in this register are NAND Flash part-dependent timing parameters specified in number of internal NAND Flash clock. For descriptions of these bits, refer to documentation on the NAND Flash part that is being implemented. B its 31:28 27:24 23:20 19:16 15:12 11:8 7:4 3:0 F ie l d trr trea tdh tds trh trp twh twp Ty p e / I n it Va l RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 D e s c r i p t io n Ready to REn Low REn Access Time Data Hold Time Data Setup Time RE Pulse Width High RE Pulse Width Low This bit must be >=1 WEn High Hold Time WEn Pulse Width This bit must be >= 2
Table 98: Timing Parameter Register 3
Offset: 0x2C
NOTE: The bits in this register are NAND Flash part-dependent timing parameters specified in number of internal NAND Flash clock. For descriptions of these bits, refer to documentation on the NAND Flash part that is being implemented. B its 31:28 27:24 23:0 F ie l d tar tclr Reserved Ty p e / I n it Va l RW 0x0 RW 0x0 RSVD 0x0 D e s c r i p t io n ALE to REn Delay CLE to REn Delay Reserved for future use
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Register Description
NAND Flash Unit
Table 99: Non-Memory Read Data Register
Offset: 0x30
B its 31:0 F ie l d read data Ty p e / I n it Va l RO 0x0 D e s c r i p t io n Returns Non-Memory Read Data
Table 100: Read ECC Generated Code Register
Offset: 0x34
B its 31:28 27:0 F ie l d Reserved gen_code Ty p e / I n it Va l RSVD 0x0 RO 0x0 D e s c r i p t io n Reserved for future use Hardware Generated ECC on Read
Table 101: Read ECC Read Code Register
Offset: 0x38
B its 31:28 27:0 F ie l d Reserved rd_code Ty p e / I n it Va l RSVD 0x0 RO 0x0 D e s c r i p t io n Reserved for future use ECC Read from NAND Device
Table 102: Read ECC Result Register
Offset: 0x3C
B its 31:18 18 F ie l d Reserved RS ECC result Ty p e / I n it Va l RSVD 0x0 RO 0x0 RO 0x0 D e s c r i p t io n Reserved for future use Reed-Solomon ECC Result 0 = No errors 1 = Errors ECC Check Result 0b00 = No error 0b01 = Error, but correctable 0b10 = Error, but not correctable 0b11 = Reserved Reserved for future use
17:16
result
15:14
Reserved
RSVD 0x0
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Table 102: Read ECC Result Register (Continued)
Offset: 0x3C
B its 13:0 F ie l d fail bit location Ty p e / I n it Va l RO 0x0 D e s c r i p t io n Failed Bit Location
Table 103: DMA Control Register
Offset: 0x40
B its 31 F ie l d DMA active Ty p e / I n it Va l RW 0x0 D e s c r i p t io n DMA Active 1 = DMA is active (nanf_dma has sole access to rd and wr buffer in nanf_if) 0 = DMA is not active (nanf_ahb_slv has sole access to rd and wr buffer) Reserved for future use DMA Operation 0 = Transfer data out of NAND controller 1 = Transfer data into NAND controller Reserved for future use DMA Data Length (in bytes, limited to page size) 0x0 = 0 bytes 0x1 = 1 bytes 0x2 = 2 bytes ... 0x840 = 2112 bytes
30 29
Reserved DMA op
RSVD RW 0x0 RSVD 0x0 RW 0x0
28:12 11:0
Reserved DMA dlen
Table 104: DMA Address Register 0
Offset: 0x44
B its 31:0 F ie l d DMA addr Ty p e / I n it Va l RW 0x0 D e s c r i p t io n DMA Address [31:0] (4-byte aligned) Address to/from which data is to transfer
Table 105: RS ECC Decode CRC Register
Offset: 0x4C
B Its 31:16 15:8 F ie l d Reserved crc_1 Ty p e / I n it Va l RSVD RO 0x0 D e s c r i p t io n Reserved for future use CRC 1
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Register Description
NAND Flash Unit
Table 105: RS ECC Decode CRC Register (Continued)
Offset: 0x4C
B Its 7:0 F ie l d crc_0 Ty p e / I n it Va l RO 0x0 D e s c r i p t io n CRC 0
Table 106: RS ECC Decode Syndrome 0 and 1 Register
Offset: 0x50
B its 31:28 27:16 15:12 11:0 F ie l d Reserved syndrome 1 Reserved syndrome 0 Ty p e / I n it Va l RSVD RO 0x0 RSVD RO 0x0 D e s c r i p t io n Reserved for future use Syndrome 1 Reserved for future use Syndrome 0
Table 107: RS ECC Decode Syndrome 2 and 3 Register
Offset: 0x54
B its 31:28 27:16 15:12 11:0 F ie l d Reserved syndrome 3 Reserved syndrome 2 Ty p e / I n it Va l RSVD RO 0x0 RSVD RO 0x0 D e s c r i p t io n Reserved for future use Syndrome 3 Reserved for future use Syndrome 2
Table 108: RS ECC Decode Syndrome 4 and 5 Register
Offset: 0x58
B its 31:28 27:16 15:12 11:0 F ie l d Reserved syndrome 5 Reserved syndrome 4 Ty p e / I n it Va l RSVD RO 0x0 RSVD RO 0x0 D e s c r i p t io n Reserved for future use Syndrome 5 Reserved for future use Syndrome 4
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Table 109: RS ECC Decode Syndrome 6 and 7 Register
Offset: 0x5C
B its 31:28 27:16 15:12 11:0 F ie l d Reserved syndrome 7 Reserved syndrome 6 Ty p e / I n it Va l RSVD RO 0x0 RSVD RO 0x0 D e s c r i p t io n Reserved for future use Syndrome 7 Reserved for future use Syndrome 6
Table 110: Control Register 4
Offset: 0x60
B its 31:9 8 F ie l d Reserved Rd_Dly_n Ty p e / I n it Va l RSVD RW 0x0 D e s c r i p t io n Reserved for future use Read Delay 1 = Do not delay read to meet NAND data out setup time requirement 0 = Delay read to meet NAND data out setup time requirement Reserved for future use
7:0
Reserved
RSVD
Table 111: NAND I/O Drive Strength Register
Offset: 0x64
B its 31:5 4:0 F ie l d Reserved Drive_strength Ty p e / I n it Va l RSVD RW 0xF D e s c r i p t io n Reserved for future use Drive Strength
Table 112: Read Data Registers
Offset: 0x1000 to 0x183C
B its 31:0 F ie l d read data Ty p e / I n it Va l RO 0x0 D e s c r i p t io n Read Data Each read retrieves 4 bytes from the read buffer. The total memory is 2112 bytes.
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Register Description
SDIO Host Controller Registers
Table 113: Write Data Registers
Offset: 0x2000 to 0x283C
B its 31:0 F ie l d write data Ty p e / I n it Va l WO 0x0 D e s c r i p t io n Write Data Each write inputs 4 bytes to the write buffer. The total memory is 2112 bytes.
3.5
SDIO Host Controller Registers
For the programmer: Note The DMA system buffer starting byte address in System Address Low Register (Table 115 p. 103) must be word (4 byte) aligned. The Block Size Register (Table 117 p. 103) only supports multiples of 4 byte block sizes (such as 4, 8, 12, 16, etc.). Once after reset, for proper set up of the I/Os, set the field in the I/O Control Register (Table 154 p. 123) to 0x0. Once after reset, to enable data CRC checking, set the field in the Command 1 Register (Table 155 p. 123) to 0x1. The timeout value ( field in the Timeout Control/Software Reset Register (Table 138 p. 113)) is off by 1. If you set this value to 0xA, it actually calculates the timeout value as if it were set to 0x9. The and fields in the Host Control Register (Table 135 p. 110) must be set by two different write actions. First set the field to the correct value and then enable by setting it to 0x1. Whenever the field in the Block Size Register (Table 117 p. 103) causes an interrupt and if this interrupt is not serviced within the data timeout intervals as specified in field in the Timeout Control/Software Reset Register (Table 138 p. 113), a timeout interrupt will occur. The SDIO registers included in this section match those provided in the SD Specification. For more information, refer to the specification: Technical Committee SD Association. SD Specifications Part A2 SD Host Controller Standard Simplified Specification Version 1.00. San Ramon, CA: SD Association, 2006. Do not write to the reserved registers in the 0x50 to 0xFA offset range.
3.5.1
Register Map
Table 114: SDIO Host Controller Register Map
R e g is t e r N a m e System Address Low Register System Address High Register Block Size Register Block Count Register Offset 0x00 0x02 0x04 0x06 Ta b l e a n d P a ge Table 115, p. 103 Table 116, p. 103 Table 117, p. 103 Table 118, p. 104
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Table 114: SDIO Host Controller Register Map (Continued)
R e g is t e r N a m e Argument Low Register Argument High Register Transfer Mode Register Command Register Response Register 0 Response Register 1 Response Register 2 Response Register 3 Response Register 4 Response Register 5 Response Register 6 Response Register 7 Buffer Data Port0 Register Buffer Data Port1 Register Present State Register 0 Present State Register 1 Host Control Register Block Gap Control Register Clock Control Register Timeout Control/Software Reset Register Normal Interrupt Status Register Error Interrupt Status Register Normal Interrupt Status Enable Register Error Interrupt Status Enable Register Normal Interrupt Status Interrupt Enable Register Error Interrupt Status Interrupt Enable Register Auto CMD12 Error Status Register Capabilities Register Capabilities Register 1 Capabilities Register 2 Capabilities Register 3 Maximum Current Register 0 Maximum Current Register 1 Maximum Current Register 2 Maximum Current Register 3 Reserved I/O Control Register Reserved Command 1 Register Offset 0x08 0x0A 0x0C 0x0E 0x10 0x12 0x14 0x16 0x18 0x1A 0x1C 0x1E 0x20 0x22 0x24 0x26 0x28 0x2A 0x2C 0x2E 0x30 0x32 0x34 0x36 0x38 0x3A 0x3C 0x40 0x42 0x44 0x46 0x48 0x4A 0x4C 0x4E 0x50 to 0x5C 0x60 0x64 to 0x68 0x6A Ta b l e a n d P a ge Table 119, p. 104 Table 120, p. 104 Table 121, p. 104 Table 122, p. 105 Table 123, p. 106 Table 124, p. 106 Table 125, p. 106 Table 126, p. 106 Table 127, p. 107 Table 128, p. 107 Table 129, p. 107 Table 130, p. 107 Table 131, p. 107 Table 132, p. 108 Table 133, p. 108 Table 134, p. 109 Table 135, p. 110 Table 136, p. 111 Table 137, p. 112 Table 138, p. 113 Table 139, p. 114 Table 140, p. 115 Table 141, p. 116 Table 142, p. 117 Table 143, p. 118 Table 144, p. 119 Table 145, p. 120 Table 146, p. 120 Table 147, p. 121 Table 148, p. 121 Table 149, p. 121 Table 150, p. 122 Table 151, p. 122 Table 152, p. 122 Table 153, p. 122 -Table 154, p. 123 -Table 155, p. 123
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Register Description
SDIO Host Controller Registers
Table 114: SDIO Host Controller Register Map (Continued)
R e g is t e r N a m e Slot Interrupt Status Register Host Control Version Register Offset 0xFC 0xFE Ta b l e a n d P a ge Table 157, p. 123 Table 158, p. 124
Table 115: System Address Low Register
Offset: 0x00
B its 15:0 F ie l d Dma_addr_l Ty p e / I n it Va l RW 0 D e s c r i p t io n 16 LSB of DMA system buffer starting byte address NOTE: The DMA system buffer starting byte address must be word (4 byte) aligned.
Table 116: System Address High Register
Offset: 0x02
B its 15:0 F ie l d Dma_addr_h Ty p e / I n it Va l RW 0 D e s c r i p t io n 16 MSB of DMA system buffer starting byte address
Table 117: Block Size Register
Offset: 0x04
B its 15 14:12 F ie l d Reserved host_dma_bdry Ty p e / I n it Va l RSVD RW D e s c r i p t io n Reserved for future use Host DMA buffer boundary. This field specifies the host memory buffer boundary. If this boundary is crossed then an interrupt(dma_int) is generated. This interrupt is reflected in field in the Normal Interrupt Status Register (Table 139 p. 114). 0x0 = 4 KB 0x1 = 8 KB 0x2 = 16 KB 0x3 = 32 KB 0x4 = 64 KB 0x5 = 128 KB 0x6 = 256 KB 0x7 = 512 KB Block Size NOTE: Block size must be a multiple of 4 bytes.
11:0
Block Size
RW 0
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Table 118: Block Count Register
Offset: 0x06
B its 15:0 F ie l d Block_count Ty p e / I n it Va l RW 0 D e s c r i p t io n The Host controller decrements the block count after each block transfer 0x1 = 1 block ... 0xFFFF = 65535 blocks The current value of block count is reflected in the Current Block Count Register.
Table 119: Argument Low Register
Offset: 0x08
B its 15:0 F ie l d Arg_l Ty p e / I n it Va l RW 0 D e s c r i p t io n 16 LSB of Command Argument This value is inserted into 48 bits command token bits[23:8].
Table 120: Argument High Register
Offset: 0x0A
B its 15:0 F ie l d Arg_h Ty p e / I n it Va l RW 0 D e s c r i p t io n 16 MSB of Command Argument This value is inserted into 48 bits command token bits[39:24].
Table 121: Transfer Mode Register
Offset: 0x0C
B its 15:6 5 4 F ie l d Reserved multi_blk_sel To_host_dir Ty p e / I n it Va l RSVD RW 0 RW 0 D e s c r i p t io n Reserved for future use This bit should be set to 1 only when multiple blocks are to be transferred. Data transfer direction select This bit defines the direction of the DAT line data transfer. The bit is set to 1 by the Host Driver to transfer data from the SD card to the SD host controller, and it is set to 0 for all other commands. Reserved for future use
3
Reserved
RSVD
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Register Description
SDIO Host Controller Registers
Table 121: Transfer Mode Register (Continued)
Offset: 0x0C
B its 2 F ie l d Auto_cmd12_en Ty p e / I n it Va l RW 0 D e s c r i p t io n Multiple block transfer for memory require CMD12 to stop the transaction. 1 = Host controller will automatically issue CMD12 when the last block transfer is completed 0 = Software is responsible for issuing cmd12 to stop the transfer and soft reset the host controller This bit validates the value in the Block Count Register (Table 118 p. 104). If PIO mode is required, this bit should be reset to 0.
1 0
blk_cnt_en dma_en
RW 0 RW 1
Table 122: Command Register
Offset: 0x0E
B its 15:14 13:8 7:6 F ie l d Reserved Cmd_index cmd_type Ty p e / I n it Va l RSVD RW 0 RW 0 D e s c r i p t io n Reserved for future use Command index These bits will be inserted into Command token bits[45:40] These bits specify the command type. 0x0 = Normal command 0x1 = Suspend command 0x2 = Resume command 0x3 = Abort command 1 = Indicates that data is present and will be transferred using the DAT line. 0 = commands using only CMD lines or commands with no data transfer but using busy signal on DAT[0] line (ex. CMD 38) Command index check enable 1 = Host controller checks the index field in the response to see if it has the same value as the command index. If it is not, it is reported as a Command Index Error. Command CRC check enable 1 = Host controller checks the CRC field in the response. If an error is detected, it is reported as a command CRC error. The number of bits checked by the CRC field value changes according to the length of response Reserved for future use
5
Data_present
RW 0
4
Cmd_index_chk_ RW en 0
3
Cmd_crc_chk_en RW 0
2
Reserved
RSVD
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Table 122: Command Register (Continued)
Offset: 0x0E
B its 1:0 F ie l d Resp_type Ty p e / I n it Va l RW 0 D e s c r i p t io n Response type select 0 = No response 1 = response length is 136 bits 2 = response length is 48 bits 3 = response length is 48 bits and check busy after resp CRC field for R3 and R4 is expected to be all 1 bits. CRC check should be disabled for these response types.
Table 123: Response Register 0
Offset: 0x10
B its 15:0 F ie l d Resp0 Ty p e / I n it Va l RO 0 D e s c r i p t io n This register contains bits[23:8] of response token.
Table 124: Response Register 1
Offset: 0x12
B its 15:0 F ie l d Resp1 Ty p e / I n it Va l RO 0 D e s c r i p t io n This register contains bits[39:24] of response token.
Table 125: Response Register 2
Offset: 0x14
B its 15:0 F ie l d Resp2 Ty p e / I n it Va l RO 0 D e s c r i p t io n For 48 bits response token, don't care For 136 bits response token, this register contains bits[55:40] of response token.
Table 126: Response Register 3
Offset: 0x16
B its 15:0 F ie l d Resp3 Ty p e / I n it Va l RO 0 D e s c r i p t io n For 48 bits response token, don't care For 136 bits response token, this register contains bits[71:56] of response token.
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Register Description
SDIO Host Controller Registers
Table 127: Response Register 4
Offset: 0x18
B its 15:0 F ie l d Resp4 Ty p e / I n it Va l RO 0 D e s c r i p t io n For 48 bits response token, don't care For 136 bits response token, this register contains bits[87:72] of response token.
Table 128: Response Register 5
Offset: 0x1A
B its 15:0 F ie l d Resp5 Ty p e / I n it Va l RO 0 D e s c r i p t io n For 48 bits response token, don't care For 136 bits response token, this register contains bits[103:88] of response token.
Table 129: Response Register 6
Offset: 0x1C
B its 15:0 F ie l d Resp6 Ty p e / I n it Va l RO 0 D e s c r i p t io n For 48 bits response token, don't care For 136 bits response token, this register contains bits[119:104] of response token. For Auto CMD12 response, this register contains bits[23:8] of response token.
Table 130: Response Register 7
Offset: 0x1E
B its 15:0 F ie l d Resp7 Ty p e / I n it Va l RO 0 D e s c r i p t io n For 48 bits response token, don't care For 136 bits response token, this register contains bits[127:120] of response token. For Auto CMD12 response, this register contains bits[39:24] of response token.
Table 131: Buffer Data Port0 Register
Offset: 0x20
B its 15:0 F ie l d Cpu_data0 Ty p e / I n it Va l RW 0 D e s c r i p t io n 16 LSB of the buffer
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Table 132: Buffer Data Port1 Register
Offset: 0x22
B its 15:0 F ie l d cpu_data1 Ty p e / I n it Va l RW 0 D e s c r i p t io n 16 MSB of the buffer
Table 133: Present State Register 0
Offset: 0x24
Host driver can get status of the Host controller from this 16-bit B its 15:12 11 F ie l d Reserved buffer_rd_en Ty p e / I n it Va l RSVD RO 0 RO 1 D e s c r i p t io n Reserved for future use This bit changes from 0x0 to 0x1 when block data is ready in the buffer. This bit changes from 0x1 to 0x0 when all the block data is read from the buffer. This bit changes from 0x0 to 0x1 when block data can be written to the buffer. So if this bit is set to 0x1, the entire block can be written to the buffer. This bit changes from 0x1 to 0x0 when all the block data is written to the buffer. Indicates read transfer is active 1 = Set: * after the end bit of the read command * when writing 1 to field in the Block Gap Control Register (Table 136 p. 112) to restart a read transfer 0 = Set: * When the last data block (as specified by block length) is transferred to the system. Transfer complete status is set to 1 if this bit is changed from 1 to 0. * When all valid data blocks have been transferred to the system and no current block transfers are being sent as a result of the field in the Block Gap Control Register (Table 136 p. 112) being set to 1. The status is set to1 if this bit is changed from 1 to 0.
10
buffer_wr_en
9
rx_active
RO 0
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Register Description
SDIO Host Controller Registers
Table 133: Present State Register 0 (Continued)
Offset: 0x24
Host driver can get status of the Host controller from this 16-bit B its 8 F ie l d tx_active Ty p e / I n it Va l RO 0 D e s c r i p t io n Indicates write transfer is active. If this bit is 0, it means no valid write data exists in the Host controller. 1 = Set: * after the end bit of the write command * when writing a 1 to field in the Block Gap Control Register (Table 136 p. 112) to restart a write transfer. This bit is cleared in the following cases: * After getting the CRC status of the last data block as specified by the transfer count (single and multiple) * After getting the CRC status of any block where data transmission is about to be stopped by a field in the Block Gap Control Register (Table 136 p. 112). A transfer complete interrupt is generated when all write data is out. Besides, during a write transaction, a Block Gap Event interrupt is generated when this bit is changed to 0, as result of the being set. This status is useful for the Host driver in determining when to issue commands during write busy. Reserved for future use This bit provides the status of the data line. 1 = Data line is in use. This bit provides the status for the driver whether it can issue a data command. 1 = It cannot issue a command that uses the data line. If this bit is 0, it indicates the CMD line is not in use, and the Host controller can issue a command using CMD line. This bit is set after the command register is written. This bit is cleared when the command response is received. Even if the cmd_inhibit_dat is set to 1, commands using only the CMD line can be issued if this bit is 0. Changing from 1 to 0 generates a command complete interrupt in the Normal Interrupt Status Register (Table 139 p. 114). If the Host controller cannot issue the command because of a command conflict err, this bit remains 1, and the command complete is not set.
7:3 2 1
Reserved dat_active cmd_inhibit_dat
RSVD RO 0 RO 0
0
Cmd_inhibit_cmd RO 0
Table 134: Present State Register 1
Offset: 0x26
B its 15:9 F ie l d Reserved Ty p e / I n it Va l RSVD D e s c r i p t io n Reserved for future use
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Table 134: Present State Register 1 (Continued)
Offset: 0x26
B its 8 F ie l d Cmd_level Ty p e / I n it Va l RO 1 RO 0xF D e s c r i p t io n CMD line Signal Level This status is used to check the CMD line level to recover from errors and for debugging. DAT[3:0] Line signal level This status is used to check the DAT line level to recover from errors and for debugging. This is especially useful in detecting the busy signal level from DAT[0]. This bit reflects the position of the write_protect latch on the SD card. This bit should be ignored if there is no such feature being provided by the card in use. Reflects the value of pin1 dat[3] line. This bit is used only for testing. 0 = Card not detected 1 = Card detected This bit is also used for testing. This bit indicates the debounced value of the card present condition. 0 = Card unstable 1 = Card stable Indicates the presence of a SD card 0 = Card not inserted 1 = Card inserted
7:4
Dat_level
3
write_prot
RO 0 RO 0
2
card_det
1
card_stable
RO 0
0
card_inserted
RO 0
Table 135: Host Control Register
Offset: 0x28
B its 15:12 11:9 F ie l d Reserved sd_bus_vlt Ty p e / I n it Va l RSVD RW 0x6 D e s c r i p t io n Reserved for future use These bits reflect the voltage at operating conditions. 0x7 = 3.3V 0x6 = 3.0V 0x5 = 1.8V 0x0 to 0x4 = Reserved This bit controls the power going out to the SD card. It will be cleared if one of the following occurs: the sd_bus_vlt and the voltage support in the Capabilities Register (Table 146 p. 120) do not match or if a card removal state was detected. Reserved for future use Extend Data Output Enable 0 = normal 1 = CMD and DATA are driven from rising edge of clock
8
sd_bus_power
RW 0
7:3 2
Reserved Hi_speed_en
RSVD RW 0
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Register Description
SDIO Host Controller Registers
Table 135: Host Control Register (Continued)
Offset: 0x28
B its 1 0 F ie l d Data_width led_ctrl Ty p e / I n it Va l RW 0 RW 0 D e s c r i p t io n 1 = 4-bit data mode 0 = 1-bit data mode, using only DAT[0] 1 = LED on 0 = LED off
Table 136: Block Gap Control Register
Offset: 0x2A
B its 15:11 10 9 8 7:4 3 F ie l d Reserved w_removal w_insertion w_card_int Reserved int_blk_gap Ty p e / I n it Va l RSVD RW 0 RW 0 RW 0 RSVD RW 0 RW 0 D e s c r i p t io n Reserved for future use 1 = Enable wakeup event on card removal detection 0 = No wakeup event 1 = Enable wakeup event on card insertion detection 0 = No wakeup event 1 = Enable wakeup event on card interrupt detection 0 = No wakeup event Reserved for future use This bit is valid only for the 4-bit mode. 1 = Enables interrupt detection at block gap for multiple block transfers If the card supports read wait, set this bit to enable use of the read wait protocol to stop read data using the DAT[2] line by Host hardware. Otherwise, Host controller has to stop SD clock to hold read data. When the Host driver detects a card insertion, it will set this bit according to the CCCR of the SDIO card. NOTE: This bit is looked at only at block gap. Within a block, hardware will stall the clock top stop read data if the host cannot accept any more data because of FIFO full, etc. NOTE: When this bit is cleared by software, operation continues. During read wait, software can issue a different cmd for different operation as long as it does not require DATA lines. When it wants to continue the waiting operation, software needs to write 0 to this register.
2
Rd_wait_ctl
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Table 136: Block Gap Control Register (Continued)
Offset: 0x2A
B its 1 F ie l d Cont_req Ty p e / I n it Va l RWAC 0 D e s c r i p t io n Continue Request This bit is used to restart a transaction which was stopped using the . To cancel stop at the block gap, set to 0 and set this bit to 1 to restart the transfer. Host controller automatically clears this bit in either of the following cases: * In the case of read transaction, the DAT Line Active changes from 0 to 1 as a read transaction restarts * In case of write transaction, the Write Transfer Active changes from 0 to 1 as the write transaction restarts Therefore, it is not necessary for the Host driver to set this bit to 0. If is set to 1, any write to this bit is ignored. Stop At block gap request This is used to stop executing a transaction at the next block gap for both DMA and non-DMA transfers. Until the transfer complete is set to 1, indicating a transfer completion, the Host driver will leave this bit set to 1. Clearing both the this bit and will not cause the transaction to restart. Read Wait is used to stop the read transaction at the block gap. The Host controller will stop the clock At Block Gap Request for write transfer, but for read transfer, it will stop the clock if is 0. Otherwise, the host controller issues a Read Wait command to stop read data.
0
Stop_at_block_ga RW p_req 0
Table 137: Clock Control Register
Offset: 0x2C
B its 15:8 F ie l d sd_freq_sel Ty p e / I n it Va l RW 0x01 D e s c r i p t io n This register selects the SD_CLK frequency. 0x00 = Use crystal clock 0x01 = Divide by 2 0x02 = Divide by 4 ... 0x80 = Divide by 256 Reserved for future use This bit controls the SD_CLK to the card. So before using the card, this bit should be set during the init phase. This bit is set to 1, once the controller detects that the internal clock is stable after setting of . This bit controls the SD_CLK of which the internal logic works on. 1 = enable clock 0 = disable
7:3 2 1 0
Reserved sd_clk_en int_clk_stable int_clk_en
RSVD RW 0 RO 0 RW 0
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Register Description
SDIO Host Controller Registers
Table 138: Timeout Control/Software Reset Register
Offset: 0x2E
B its 15:11 10 9 8 F ie l d Reserved sw_rst_dat sw_rst_cmd sw_rst_all Ty p e / I n it Va l RSVD RWAC 0 RWAC 0 RWAC 0 RSVD RW 0xE D e s c r i p t io n Reserved for future use Soft reset for the data part of logic Soft reset for the cmd part of logic Software Reset For All This reset affects the status, state machine, and FIFOs synchronously. Reserved for future use Determines the interval by which DAT line timeouts are detected. This timeout is initiated in the following cases: For read transaction, waiting for data from cards. This is referred to as NAC timing value in the SD specification, which specifies the maximum timing from read command to read data (card data access time). For write transaction, waiting for data from IMB slave, IMB Master, or CPU. 0x0 = SD_CLK x 2^13 0x1 = SD_CLK x 2^14 ... 0xE = SD_CLK x 2^27 0xF = Reserved For other transactions, there are fixed timeouts defined as follows (unit in TIMEOUT_CLK cycles) On the card: NCR = 64, maximum timing value from command to response. NID = 64 (5 in specification), maximum timing value from command to OCR response On the Host: NRC = 8, minimum timing value from response to next command NCC = 8, minimum timing value from command to next command. NWR = 2, minimum timing value from data CRC status (from card in write transaction) to next write data in multiple write blocks NST = 2, minimum timing from STOP command to end of write data Refer to the SD specification for more information on these fixed values.
7:4 3:0
Reserved Timeout_value
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88ALP01 Datasheet
Table 139: Normal Interrupt Status Register
Offset: 0x30
B its 15 F ie l d Err_int Ty p e / I n it Va l RO 0 RSVD RW1C 0 RW1C 0 RW1C 0 RW1C 0 RW1C 1 RW1C 0 D e s c r i p t io n Error interrupt If any of bits in the Error Interrupt Status Register (Table 140 p. 115) are set, then this bit is set. Reserved for future use Card interrupt 1 = Host controller detects an interrupt from the Card This bit is set when a card removal event is detected. This bit is set when a card insertion event is detected. This status is set if the field in the Present State Register 0 (Table 133 p. 108) changes from 0x0 to 0x1. This status is set if the field in the Present State Register 0 (Table 133 p. 108) changes from 0x0 to 0x1. DMA interrupt This status is set if the Host Controller detects DMA crossing over the host_dma_buf_bndry as specified in Block Size Register (Table 117 p. 103). Block Gap Event If the field in the Block Gap Control Register (Table 136 p. 112) is set, this bit is set when both a read/write transaction is stopped at a block gap. If the field is not set to 1, this bit is not set to 1. Transfer Complete This bit is set when a read/write transaction is completed For read transaction, this bit is set at the falling edge of Read Transfer Active Status. There are two cases in which this occurs: * data transfer is completed as specified by data length. * data stopped at the block gap and completed data transfer by setting the field in the Block Gap Control Register (Table 136 p. 112) field. For write transaction, this bit is set at the falling edge of the DAT Line Active status. There are two cases in which this occurs: * data transfer is completed as specified by data length and the busy signal released. * data stopped at the block gap and completed data transfer by setting the field
14:9 8 7 6 5
Reserved Card_int card_rem_int card_ins_int Rx_rdy
4
Tx_rdy
3
Dma_int
2
Block_gap_evt
RW1C 0
1
Xfer_complete
RW1C 0
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Register Description
SDIO Host Controller Registers
Table 139: Normal Interrupt Status Register (Continued)
Offset: 0x30
B its 0 F ie l d Cmd_complete Ty p e / I n it Va l RW1C 0 D e s c r i p t io n Command Complete This bit is set when the end bit of the command response (Except Auto CMD12) is received. Note that Command Timeout Error has higher priority than Command complete.
Table 140: Error Interrupt Status Register
Offset: 0x32
B its 15 14 13 12 11:9 8 F ie l d CRC status err Crc_start_bit_err Crc_end_bit_err Resp_t_bit_err Reserved Auto_cmd12_err Ty p e / I n it Va l RW1C 0 RW1C 0 RW1C 0 RW1C 0 RSVD RW1C 0 D e s c r i p t io n CRC status returned from card is not good in write transaction. CRC status s start bit is not at expected logic level in write transaction CRC status s end bit is not at expected logic level in write transaction Response Transmission bit error Reserved for future use Auto CMD12 Error Occurs when detecting that one of the bits in Auto CMD12 Error Status Register (Table 145 p. 120) has changed from 0 to 1. This feature is not supported and this bit will always be read as 0. ReadData End Bit Error 1 = 0 detected at the end bit position of read data which uses the DAT line or at the end bit position of the CRC status Read Data CRC error 1 = read data which uses the DAT line transferred or Write CRC status having a value other than 010 detected Data timeout Error This bit is set when one of the following is detected: * Busy timeout after Write CRC status * Write CRC status timeout * Read Data timeout Command Index Error This bit is set when a command index error occurs in the command response
7 6
cur_limit_err
RW1C 0
Rd_Data_end_bit RW1C _err 0
5
Rd_Data_crc_err RW1C 0 Data_timeout_err RW1C 0
4
3
Cmd_index_err
RW1C 0
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88ALP01 Datasheet
Table 140: Error Interrupt Status Register (Continued)
Offset: 0x32
B its 2 F ie l d Ty p e / I n it Va l D e s c r i p t io n Command End Bit Error This bit is set when detecting that the end bit of a command response is 0. Command CRC Error This bit is set in two cases: * A CRC error is detected in the command response * The Host controller detects a CMD line conflict by monitoring the CMD line when a command is issued. The Host controller will abort the command (stops driving CMD line). The will also be set to 1 to distinguish CMD line conflict. Command Timeout Error This bit is set when no response is returned within 64 SD_CLK cycles from the end bit of the command.
Cmd_end_bit_err RW1C 0 Cmd_crc_err RW1C 0
1
0
Cmd_timeout_err RW1C 0
Table 141: Normal Interrupt Status Enable Register
Offset: 0x34
B its 15:9 8 F ie l d Reserved Card_int_en Ty p e / I n it Va l RSVD RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 D e s c r i p t io n Reserved for future use Card interrupt enable 0 = disabled 1 = enabled Card removal status enable Card insertion status enable Buffer Read Ready Enable 0 = disabled 1 = enabled Buffer Write Ready Enable 0 = disabled 1 = enabled DMA interrupt Enable 0 = disabled 1 = enabled Block Gap Event Enable 0 = disabled 1 = enabled Transfer Complete Enable 0 = disabled 1 = enabled
7 6 5
card_rem_en card_ins_en rd_rdy_en
4
tx_rdy_en
3
Dma_int_en
2
Block_gap_evt_e RW n 0 Xfer_complete_e RW n 0
1
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Register Description
SDIO Host Controller Registers
Table 141: Normal Interrupt Status Enable Register (Continued)
Offset: 0x34
B its 0 F ie l d Ty p e / I n it Va l D e s c r i p t io n Command Complete Enable 0 = disabled 1 = enabled
Cmd_complete_e RW n 0
Table 142: Error Interrupt Status Enable Register
Offset: 0x36
B its 15 F ie l d CRC status err_en Ty p e / I n it Va l RW 0 D e s c r i p t io n CRC_status_err Enable 0 = disabled 1 = enabled CRC status start bit err Enable 0 = disabled 1 = enabled CRC status end bit err Enable 0 = disabled 1 = enabled Response Transmission bit error Enable 0 = disabled 1 = enabled Reserved for future use Auto CMD12 Error Enable 0 = disabled 1 = enabled Current limit error enable Data End Bit Error Enable 0 = disabled 1 = enabled Data CRC error Enable 0 = disabled 1 = enabled Data Timeout Error Enable 0 = disabled 1 = enabled Command Index Error Enable 0 = disabled 1 = enabled Command End Bit Error Enable 0 = disabled 1 = enabled
14
Crc_start_err_en RW 0 Crc_end_err_en RW 0
13
12
Resp_t_bit_err_e RW n 0 Reserved RSVD
11:9 8
Auto_cmd12_err_ RW en 0 cur_lim_err_en RW 0
7 6
Rd_Data_end_bit RW _err_en 0 Rd_data_crc_err_ RW en 0 Data_timeout_err RW _en 0 Cmd_index_err_e RW n 0 Cmd_end_bit_err RW _en 0
5
4
3
2
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88ALP01 Datasheet
Table 142: Error Interrupt Status Enable Register (Continued)
Offset: 0x36
B its 1 F ie l d Cmd_crc_err_en Ty p e / I n it Va l RW 0 D e s c r i p t io n Command CRC Error Enable 0 = disabled 1 = enabled Command Timeout Error Enable 0 = disabled 1 = enabled
0
Cmd_timeout_err RW _en 0
Table 143: Normal Interrupt Status Interrupt Enable Register
Offset: 0x38
B its 15:9 8 F ie l d Reserved Card_int_int_en Ty p e / I n it Va l RSVD RW 0 D e s c r i p t io n Reserved for future use Card interrupt Interrupt Enable 0 = disabled 1 = enabled Card removal interrupt enable Card insertion interrupt enable Buffer Read Ready Interrupt Enable 0 = disabled 1 = enabled Buffer Write Ready Interrupt Enable 0 = disabled 1 = enabled DMA interrupt Interrupt Enable 0 = disabled 1 = enabled Block Gap Event Interrupt Enable 0 = disabled 1 = enabled Transfer Complete Interrupt Enable 0 = disabled 1 = enabled Command Complete Interrupt Enable 0 = disabled 1 = enabled
7 6 5
card_rem_int_en RW 0 card_ins_int_en rx_rdy_int_en RW 0 RW 0 RW 0 RW 0
4
tx_rdy_int_en
3
Dma_int_int_en
2
Block_gap_evt_in RW t_en 0 Xfer_complete_in RW t_en 0 Cmd_complete_i RW nt_en 0
1
0
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Register Description
SDIO Host Controller Registers
Table 144: Error Interrupt Status Interrupt Enable Register
Offset: 0x3A
B its 15 F ie l d CRC status err_int_en Ty p e / I n it Va l RW 0 D e s c r i p t io n CRC status err interrupt Enable 0 = disabled 1 = enabled CRC status start bit err interrupt Enable 0 = disabled 1 = enabled CRC status end bit err interrupt Enable 0 = disabled 1 = enabled Response Transmission bit error interrupt Enable 0 = disabled 1 = enabled Reserved for future use Auto CMD12 Error Interrupt Enable 0 = disabled 1 = enabled Current limit error interrupt enable. Data End Bit Error Interrupt Enable 0 = disabled 1 = enabled Data CRC error Interrupt Enable 0 = disabled 1 = enabled Data Timeout Error Interrupt Enable 0 = disabled 1 = enabled Command Index Error Interrupt Enable 0 = disabled 1 = enabled Command End Bit Interrupt Error Enable 0 = disabled 1 = enabled Command CRC Error Interrupt Enable 0 = disabled 1 = enabled Command Timeout Error Interrupt Enable 0 = disabled 1 = enabled
14
Crc_start_bit_err_ RW int_en 0 Crc_end_bit_err_i RW nt_en 0 Resp_t_bit_err_in RW t_en 0 Reserved RSVD
13
12
11:9 8
Auto_cmd12_err_ RW int_en 0 cur_lim_err_int_e RW n 0 Rd_Data_end_bit RW _err_int_en 0 Rd_Data_crc_err RW _int_en 0 Data_timeout_err RW _int_en 0 Cmd_index_err_i RW nt_en 0 Cmd_end_bit_err RW _int_en 0 Cmd_crc_err_int_ RW en 0 Cmd_timeout_err RW _int_en 0
7 6
5
4
3
2
1
0
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88ALP01 Datasheet
Table 145: Auto CMD12 Error Status Register
Offset: 0x3C
B its 15:8 7 6:5 4 F ie l d Reserved cmd_not_issued Reserved Ty p e / I n it Va l RSVD ROC 0 RSVD D e s c r i p t io n Reserved for future use Command not issued because of auto_cmd12 error. Reserved for future use Occurs if the command index error occurs in response to a command 0 = disabled 1 = enabled Occurs when detecting that the end bit of command response is 0 0 = disabled 1 = enabled Occurs when detecting CRC error in the command response 0 = disabled 1 = enabled Occurs if no response is returned within 64 SD_CLK cycles from the end bit of command. 0 = disabled 1 = enabled Occurs when host controller cannot issue Auto cmd12 to stop multiple block data transfer due to some errors. 0 = disabled 1 = enabled
Auto_cmd12_ind RW1C ex_err 00
3
Auto_cmd12_end RW1C _bit_err 00
2
Auto_cmd12_crc RW1C _err 0
1
Auto_cmd12_tim RW1C eout_err 0
0
Auto_cmd12_not RW1C _exe 0
Table 146: Capabilities Register
Offset: 0x40
B its 15:14 13:8 7 F ie l d Reserved base_freq timeout_unit Ty p e / I n it Va l RSVD RW 0x30 RW 1 RSVD RW 0x30 D e s c r i p t io n Reserved for future use The base clock frequency for SD_CLK The unit of base clock used to detect timeouts. 1 = MHz 0 = kHz Reserved for future use This value indicates the base clock frequency used to detect timeouts.
6 5:0
Reserved timeout_freq
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Register Description
SDIO Host Controller Registers
Table 147: Capabilities Register 1
Offset: 0x42
NOTE: The values in this register are initialized by hardware. Use caution when writing to these bits. B its 15:11 10 F ie l d Reserved vlt_18 Ty p e / I n it Va l RSVD RW 0 RW 1 RW 1 RW 1 RW 1 RW 1 RSVD RW 00 D e s c r i p t io n Reserved for future use 1.8V support 1 = 1.8V supported 0 = 1.8V not supported 3.0V support 1 = 3.0V supported 0 = 3.0V not supported. 3.3V support 1 = 3.3V supported 0 = 3.3V not supported Suspend/Resume support 1 = Supported 0 = Not supported. DMA Support 1 = Supported 0 = Not supported High Speed support 1 = Supported 0 = Not supported Reserved for future use Maximum block length supported by controller 0x0 = 512 bytes 0x1 = 1024 bytes 0x2 = 2048 bytes 0x3 = Reserved
9
vlt_30
8
vlt_33
7
sus_res_support
6
dma_support
5
Hi_spd_support
4:2 1:0
Reserved max_blk_len
Table 148: Capabilities Register 2
Offset: 0x44
B its 15:0 F ie l d Reserved Ty p e / I n it Va l RSVD D e s c r i p t io n Reserved for future use
Table 149: Capabilities Register 3
Offset: 0x46
B its 15:0 F ie l d Reserved Ty p e / I n it Va l RSVD D e s c r i p t io n Reserved for future use
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88ALP01 Datasheet
Table 150: Maximum Current Register 0
Offset: 0x48
NOTE: The values in this register are initialized by hardware. Use caution when writing to these bits. B its 15:8 F ie l d max_cur_30 Ty p e / I n it Va l RW 0 D e s c r i p t io n Maximum current for 3.0V 0x0 = Get information via another method. 0x1 = 4 ma 0x2 = 8 ma ... 0xF = 1020 ma Maximum current for 3.3V 0x0 = Get information via another method. 0x1 = 4 ma 0x2 = 8 ma ... 0xF = 1020 ma
7:0
max_cur_33
RW 0
Table 151: Maximum Current Register 1
Offset: 0x4A
B its 15:8 7:0 F ie l d Reserved max_cur_18 Ty p e / I n it Va l RSVD RW 0 D e s c r i p t io n Reserved for future use Maximum current for 3.3V 0 = Get information via another method. 1 = 4ma 2 = 8ma ... 255 = 1020ma
Table 152: Maximum Current Register 2
Offset: 0x4C
B its 15:0 F ie l d Reserved Ty p e / I n it Va l RSVD D e s c r i p t io n Reserved for future use
Table 153: Maximum Current Register 3
Offset: 0x4E
B its 15:0 F ie l d Reserved Ty p e / I n it Va l RSVD D e s c r i p t io n Reserved for future use
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Register Description
SDIO Host Controller Registers
Table 154: I/O Control Register
Offset: 0x60
B its 15 F ie l d data3_iddqn Ty p e / I n it Va l RW 1 RSVD D e s c r i p t io n Data 3 Pull Up/Pull Down 0 = Disable 1 = Enable Reserved for future use
14:0
Reserved
Table 155: Command 1 Register
Offset: 0x6A
B its 15:3 2 F ie l d Reserved crc16_chk_en Ty p e / I n it Va l RSVD RW 0 RSVD D e s c r i p t io n Reserved for future use Enable data crc16 check 0 = Data crc16 check disabled 1 = Data crc16 check enabled Reserved for future use
1:0
Reserved
Table 156: SD Drive Strength Register
Offset: 0x7C
B its 15:11 10:8 7:3 2:0 F ie l d Reserved Ty p e / I n it Va l RSVD D e s c r i p t io n Reserved for future use P Level Drive Strength Value Reserved for future use N Level Drive Strength Value
SD_Drive_Streng RW th_P 0x7 Reserved RSVD
SD_Drive_Streng RW th_N 0x7
Table 157: Slot Interrupt Status Register
Offset: 0xFC
B its 15:1 0 F ie l d Reserved slot_int Ty p e / I n it Va l RSVD RO 0 D e s c r i p t io n Reserved for future use Interrupt line
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88ALP01 Datasheet
Table 158: Host Control Version Register
Offset: 0xFE
NOTE: The values in this register are initialized by hardware. Use caution when writing to these bits. B its 15:8 7:0 F ie l d vendor_ver sd_ver Ty p e / I n it Va l RW 0 RW 0x0 D e s c r i p t io n Marvell specific version number SD Host specification number 0 = Supports version 1.0 All other values are reserved.
3.6
3.6.1
CMOS Camera Interface Controller
Register Map
Table 159: CMOS Camera Interface Controller Register Map
R e g is t e r N a m e Y0-Base Address Register Y1-Base Address Register Y2-Base Address Register U0-Base Address Register U1-Base Address Register U2-Base Address Register V0-Base Address Register V1-Base Address Register V2-Base Address Register Image Pitch Register IRQ RAW Status Register IRQ Mask Register IRQ Status Register Image Size Register Image Offset Register Control 0 Register Control 1 Register Reserved Clock Control Register SRAM TC0 Register (Test Only) SRAM TC1 Register (Test Only) Reserved General Purpose (GPR) Register TWSI Control 0 Register Offset 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C 0x40 0x44 to 0x84 0x88 0x8C 0x90 0x88 to 0xB0 0xB4 0xB8 Ta b l e a n d P a ge Table 160, p. 125 Table 161, p. 125 Table 162, p. 125 Table 163, p. 126 Table 164, p. 126 Table 165, p. 126 Table 166, p. 126 Table 167, p. 127 Table 168, p. 127 Table 169, p. 127 Table 170, p. 127 Table 171, p. 128 Table 172, p. 129 Table 173, p. 131 Table 174, p. 131 Table 175, p. 132 Table 176, p. 135 -Table 177, p. 136 Table 178, p. 137 Table 179, p. 137 -Table 180, p. 137 Table 181, p. 138
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Register Description
CMOS Camera Interface Controller
Table 159: CMOS Camera Interface Controller Register Map (Continued)
R e g is t e r N a m e TWSI Control 1 Register Reserved Offset 0xBC 0xC0 Ta b l e a n d P a ge Table 182, p. 139 --
3.6.2
Register Descriptions
When the output format is RGB or YCbCr packed, only the following registers must be programmed: Y0-Base Address Register, Y1-Base Address Register, and Y2-Base Address Register. When the output format is YCbCr planar, Y0-Base Address Register through V2-Base Address Register must be programmed.
Note
Table 160: Y0-Base Address Register
Offset: 0x00
B its 31:2 1:0 F ie l d YBASE0 YBASE0 Ty p e / I n it Va l RW 0x0 RO 0x0 D e s c r i p t io n Y0 Base Address bit [31:2] Y0 Base Address bit [1:0]
Table 161: Y1-Base Address Register
Offset: 0x04
B its 31:2 1:0 F ie l d YBASE1 YBASE1 Ty p e / I n it Va l RW 0x0 RO 0x0 D e s c r i p t io n Y1 Base Address bit [31:2] Y1 Base Address bit [1:0]
Table 162: Y2-Base Address Register
Offset: 0x08
B its 31:2 1:0 F ie l d YBASE2 YBASE2 Ty p e / I n it Va l RW 0x0 RO 0x0 D e s c r i p t io n Y2 Base Address bit [31:2] Y2 Base Address bit [1:0]
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88ALP01 Datasheet
Table 163: U0-Base Address Register
Offset: 0x0C
B its 31:2 1:0 F ie l d UBASE0 UBASE0 Ty p e / I n it Va l RW 0x0 RO 0x0 D e s c r i p t io n U0 Base Address bit [31:2] U0 Base Address bit [1:0]
Table 164: U1-Base Address Register
Offset: 0x10
B its 31:2 1:0 F ie l d UBASE1 UBASE1 Ty p e / I n it Va l RW 0x0 RO 0x0 D e s c r i p t io n U1 Base Address for bit [31:2] U1 Base Address for bit [1:0]
Table 165: U2-Base Address Register
Offset: 0x14
B its 31:2 1:0 F ie l d UBASE2 UBASE2 Ty p e / I n it Va l RW 0x0 RO 0x0 D e s c r i p t io n U2 Base Address bit [31:2] U2 Base Address bit [1:0]
Table 166: V0-Base Address Register
Offset: 0x18
B its 31:2 1:0 F ie l d VBASE0 VBASE0 Ty p e / I n it Va l RW 0x0 RO 0x0 D e s c r i p t io n V0 Base Address bit [31:2] V0 Base Address bit [1:0]
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Register Description
CMOS Camera Interface Controller
Table 167: V1-Base Address Register
Offset: 0x1C
B its 31:2 1:0 F ie l d VBASE1 VBASE1 Ty p e / I n it Va l RW 0x0 RO 0x0 D e s c r i p t io n V1 Base Address bit [31:2] V1 Base Address bit [1:0]
Table 168: V2-Base Address Register
Offset: 0x20
B its 31:2 1:0 F ie l d VBASE2 VBASE2 Ty p e / I n it Va l RW 0x0 RO 0x0 D e s c r i p t io n V2 Base Address bit [31:2] V2 Base Address bit [1:0]
Table 169: Image Pitch Register
Offset: 0x24
B its 31:30 29:18 F ie l d Reserved UVPITCH Ty p e / I n it Va l RO 0x0 RW( 0x0 RO( 0x0 RW 0x0 RO 0x0 D e s c r i p t io n Reserved UV Pitch (distance in unit of 32-bit between two vertically adjacent pixels). Must be programmed when output format is YUV Planar. Reserved Y Pitch (distance in unit of 32-bit between two vertically adjacent pixels). Reserved
17:14 13:2 1:0
Reserved YPITCH Reserved
Table 170: IRQ RAW Status Register
Offset: 0x28
B its 31:19 F ie l d Reserved Ty p e / I n it Va l RO 0x0 D e s c r i p t io n Reserved
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88ALP01 Datasheet
Table 170: IRQ RAW Status Register (Continued)
Offset: 0x28
B its 18 F ie l d TWSIEIRQR Ty p e / I n it Va l RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 D e s c r i p t io n TWSI Error IRQ 0 = No interrupt (Default) 1 = TWSI Error TWSI Read IRQ 0 = No interrupt (Default) 1 = Read data from Sensor is available TWSI Write IRQ 0 = No interrupt (Default) 1 = Write to Sensor is done Reserved FIFO Full (Overflow) IRQ 0 = No interrupt (Default) 1 = FIFO Overflow occurs Start of Frame 2 IRQ 0 = No interrupt (Default) 1 = Starting to write frame #2 Start of Frame 1 IRQ 0 = No interrupt (Default) 1 = Starting to write frame #1 Start of Frame 0 IRQ 0 = No interrupt (Default) 1 = Starting to write frame #0 End of Frame 2 IRQ 0 = No interrupt (Default) 1 = Done writing complete frame #2 End of Frame 1 IRQ 0 = No interrupt (Default) 1 = Done writing complete frame #1 End of Frame 0 IRQ 0 = No interrupt (Default) 1 = Done writing complete frame #0
17
TWSIRIRQR
16
TWSIWIRQR
15:7 6
Reserved FIFOFULLIRQR
5
SOF2IRQR
4
SOF1IRQR
3
SOF0IRQR
2
EOF2IRQR
1
EOF1IRQR
0
EOF0IRQR
Table 171: IRQ Mask Register
Offset: 0x2C
B its 31:19 F ie l d Reserved Ty p e / I n it Va l RW 0x0 D e s c r i p t io n Reserved
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Register Description
CMOS Camera Interface Controller
Table 171: IRQ Mask Register (Continued)
Offset: 0x2C
B its 18 F ie l d TWSIEIRQM Ty p e / I n it Va l RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 D e s c r i p t io n TWSI Error IRQ 0 = Disable Interrupt (Default) 1 = Enable Interrupt TWSI Read IRQ 0 = Disable Interrupt (Default) 1 = Enable Interrupt TWSI Write IRQ 0 = Disable Interrupt (Default) 1 = Enable Interrupt Reserved FIFO Full (Overflow) IRQ 0 = Disable Interrupt (Default) 1 = Enable Interrupt Start of Frame 2 IRQ 0 = Disable Interrupt (Default) 1 = Enable Interrupt Start of Frame 1 IRQ 0 = Disable Interrupt (Default) 1 = Enable Interrupt Start of Frame 0 IRQ 0 = Disable Interrupt (Default) 1 = Enable Interrupt End of Frame 2 IRQ 0 = Disable Interrupt (Default) 1 = Enable Interrupt End of Frame 1 IRQ 0 = Disable Interrupt (Default) 1 = Enable Interrupt End of Frame 0 IRQ 0 = Disable Interrupt (Default) 1 = Enable Interrupt
17
TWSIRIRQM
16
TWSIWIRQM
15:7 6
Reserved FIFOFULLIRQM
5
SOF2IRQM
4
SOF1IRQM
3
SOF0IRQM
2
EOF2IRQM
1
EOF1IRQM
0
EOF0IRQM
Table 172: IRQ Status Register
Offset: 0x30
B its 31:19 F ie l d Reserved Ty p e / I n it Va l RO 0x0 D e s c r i p t io n Reserved
Copyright (c) 2007 Marvell July 17, 2007, Preliminary Document Classification: Proprietary Information
Doc. No. MV-S103921-00 Rev. - Page 129
88ALP01 Datasheet
Table 172: IRQ Status Register (Continued)
Offset: 0x30
B its 18 F ie l d TWSIEIRQS Ty p e / I n it Va l RO 0x0 D e s c r i p t io n TWSI Error IRQ read 0 = No interrupt read 1 = Interrupt is asserted write 0 = No effect write 1 = Clear interrupt TWSI Read IRQ read 0 = No interrupt read 1 = Interrupt is asserted write 0 = No effect write 1 = Clear interrupt TWSI Write IRQ read 0 = No interrupt read 1 = Interrupt is asserted write 0 = No effect write 1 = Clear interrupt Reserved FIFO Full (Overflow) IRQ read 0 = No interrupt read 1 = Interrupt is asserted write 0 = No effect write 1 = Clear interrupt Start of Frame 2 IRQ read 0 = No interrupt read 1 = Interrupt is asserted write 0 = No effect write 1 = Clear interrupt Start of Frame 1 IRQ read 0 = No interrupt read 1 = Interrupt is asserted write 0 = No effect write 1 = Clear interrupt Start of Frame 0 IRQ read 0 = No interrupt read 1 = Interrupt is asserted write 0 = No effect write 1 = Clear interrupt End of Frame 2 IRQ read 0 = No interrupt read 1 = Interrupt is asserted write 0 = No effect write 1 = Clear interrupt
17
TWSIRIRQS
RO 0x0
16
TWSIWIRQS
RO 0x0
15:7 6
Reserved FIFOFULLIRQS
RO 0x0 RO 0x0
5
SOF2IRQS
RO 0x0
4
SOF1IRQS
RO 0x0
3
SOF0IRQS
RO 0x0
2
EOF2IRQS
RO 0x0
Doc. No. MV-S103921-00 Rev. - Page 130 Document Classification: Proprietary Information
Copyright (c) 2007 Marvell July 17, 2007, Preliminary
Register Description
CMOS Camera Interface Controller
Table 172: IRQ Status Register (Continued)
Offset: 0x30
B its 1 F ie l d EOF1IRQS Ty p e / I n it Va l RO 0x0 D e s c r i p t io n End of Frame 1 IRQ read 0 = No interrupt read 1 = Interrupt is asserted write 0 = No effect write 1 = Clear interrupt End of Frame 0 IRQ read 0 = No interrupt read 1 = Interrupt is asserted write 0 = No effect write 1 = Clear interrupt
0
EOF0IRQS
RO 0x0
Table 173: Image Size Register
Offset: 0x34
B its 31:29 28:16 15:14 13:0 F ie l d Reserved VSIZE Reserved HSIZE Ty p e / I n it Va l RO 0x0 RW 0x0 RO 0x0 RW 0x0 D e s c r i p t io n Reserved Image length in scanline Reserved Image width in PIXCLK unit
Table 174: Image Offset Register
Offset: 0x38
B its 31:29 28:16 F ie l d Reserved VOFF Ty p e / I n it Va l RO 0x0 RW 0x0 D e s c r i p t io n Reserved Image line offset in scanline Starts capturing external CMOS sensor image at VOFF line. 0 = CCIC starts capturing at line #0 for every frame Reserved Image pixel offset in PIXCLK Starts capturing external CMOS sensor image at HOFF pixel. 0 = CCIC starts capturing at pixel #0 for every line in the frame.
15:14 13:0
Reserved HOFF
RO 0x0 RW 0x0
Copyright (c) 2007 Marvell July 17, 2007, Preliminary Document Classification: Proprietary Information
Doc. No. MV-S103921-00 Rev. - Page 131
88ALP01 Datasheet
Table 175: Control 0 Register
Offset: 0x3C
B its 31:30 F ie l d SIFMODE Ty p e / I n it Va l RW 0x0 D e s c r i p t io n Sensor Interface Mode 00 = Master mode with hsync/vsync (Default) 01 = Master mode without hsync/vsync (BT 656) Others = Reserved Down Scaler 000 = Disable (Default) 001 = 1:2 scale down Others = Reserved Down Scale is not supported when = 00 (YCbCr) and = 100 (YCbCr 422). VCLK Polarity with respect to data sampling 0 = Sample CMOS Sensor Data at rising-edge of VCLK (Default) 1 = Sample CMOS Sensor Data at falling-edge of VCLK CMOS Sensor VSYNC Polarity 0 = Active high (Default) 1 = Active low CMOS Sensor HSYNC Polarity 0 = Active high (Default) 1 = Active low Reserved for future use YCbCr Endianness Format when = 101, this bit defines the Endianness of the external CMOS sensor's output (CCIC's input). {MSB:LSB}: 00 = Y1CbY0Cr (Default) 01 = Y1CrY0Cb 10 = CrY1CbY0 11 = CbY1CrY0 when = 100, this bit controls byte swapping before data is written to memory: 00 = no byte swapping 01 = swap 1st and 3rd byte 10 = swap 2nd and 4th byte 11 = swap 1st and 3rd byte, 2nd and 4th byte 15:13 YUVOUTFMT RW 0x0 YCbCr Output Format 000 = 422 8 bpp planar (Default) 100 = 422 8 bpp packed 101 = 420 8 bpp planar Others = Reserved
29:27
DSCALE
RW 0x0
26
VCLKPOL
RW 0x0
25
VPOL
RW 0x0 RW 0x0 RSVD RW 0x0
24
HPOL
23:18 17:16
Reserved YUVENDFMT
Doc. No. MV-S103921-00 Rev. - Page 132 Document Classification: Proprietary Information
Copyright (c) 2007 Marvell July 17, 2007, Preliminary
Register Description
CMOS Camera Interface Controller
Table 175: Control 0 Register (Continued)
Offset: 0x3C
B its 12 F ie l d RGBOUTEND Ty p e / I n it Va l RW 0x0 RW 0x0 D e s c r i p t io n RGB Output Endianness 0 = MSB: Blue, LSB: Red (Default) 1 = MSB: Red, LSB: Blue RGB Input and Output Format (when = RGB) Defines the CCIC's input (CMOS Sensor's output) and the CCIC's output RGB format. 000 = 565 (Default) 001 = 555 100 = 444 Others = Reserved CCIC's Output Data Format 00 = YCbCr (Default) 01 = RGB 10 = Bayer 11 = Reserved NOTE: Possible values of DOUTFMT based on : DINFMT = 00, DOUTFMT = 00 DINFMT = 01, DOUTFMT = 01 DINFMT = 10, DOUTMFT = 10 CCIC's Input Data Format (CMOS Sensor's Output Data Format) 00 = YCbCr (Default) 01 = RGB 10 = Bayer 11 = Reserved Reserved
11:9
RGBINOUTFMT
8:7
DOUTFMT
RW 0x0
6:5
DINFMT
RW 0x0
4
Reserved
RW( 0x0
Copyright (c) 2007 Marvell July 17, 2007, Preliminary Document Classification: Proprietary Information
Doc. No. MV-S103921-00 Rev. - Page 133
88ALP01 Datasheet
Table 175: Control 0 Register (Continued)
Offset: 0x3C
B its 3:2 F ie l d RGBENDFMT Ty p e / I n it Va l RW 0x0 D e s c r i p t io n RGB Endianness Format When = 000 (RGB 565) < R G B E N C M O S S e ns o r O u tp u t DFMT> F ir s t B y te Se c o n d B y t e 00 01 10 11 {Red[7:3], Green[7:5]} {Green[4:2], Red[7:3]} {Green[4:2], Blue[7:3]} {Blue[7:3], Green[7:5]} {Green[4:2], Blue[7:3]} {Blue[7:3], Green[7:5]} {Red[7:3], Green[7:5]} {Green[4:2], Red[7:3]}
When = 100 (RGB 444) < R G B E N C M O S S e ns o r O u tp u t DFMT> F ir s t B y te Se c o n d B y t e 00 01 10 11 {Red[7:4], Green[7:4]} {0000, Red[7:4]} {Blue[7:4], Green[7:4]} {0000, Blue[7:4]} {Blue[7:4], 0000} {Green[7:4], Blue[7:4]} {Red[7:4], 0000} {Green[7:4], Red[7:4]}
When = 001 (RGB 555) < R G B E N C M O S S e ns o r O u tp u t DFMT> F ir s t B y te Se c o n d B y t e 00 01 10 11 {Red[7:3], Green[7:5]} {0, Red[7:3], Green[7:6]} {Blue[7:3], Green[7:5]} {0, Blue[7:3], Green[7:6]} {Green[4:3], Blue[7:3], 0} {Green[5:3], Blue[7:3]} {Green[4:3], Red[7:3], 0} {Green[5:3], Red[7:3]}
1
DSTOPSEL
RW 0x0
Panasonic DSTOP Select Reserved
Doc. No. MV-S103921-00 Rev. - Page 134 Document Classification: Proprietary Information
Copyright (c) 2007 Marvell July 17, 2007, Preliminary
Register Description
CMOS Camera Interface Controller
Table 175: Control 0 Register (Continued)
Offset: 0x3C
B its 0 F ie l d EN Ty p e / I n it Va l RW 0x0 D e s c r i p t io n CCIC Enable Write 1 only after all registers have been initialized to proper values. 0 = Disable (Default) 1 = Enable
Table 176: Control 1 Register
Offset: 0x40
B its 31:30 29 F ie l d Reserved BUSCLKG Ty p e / I n it Va l RW 0x0 RW 0x0 D e s c r i p t io n Reserved Bus Clock gating control (test only) 0 = CCIC's DMA Clock is always free running (Default) 1 = CCIC's DMA Clock is automatically gated when not in use Power Down Enable 0 = Normal Operation 1 = Power Down. External Sensor is assumed to be in power-off state. All CCIC's output PADs are tristated. All CCIC's input PADs are gated. The actual tristating and gating of the PADs is only done when external sensor power is off, which is controlled by GPIO. Frame Number Select Controls the number of CCIC's "ping-pong" buffers. 0 = 3 Frames 1 = 2 Frames DMA Burst Size Select 00 = Burst of 32-byte 01 = Burst of 16-byte 10 = Burst of 64-byte (Recommended) 11 = Reserved YUV 420 Select 0 = Drop Odd Line 1 = Drop Even Line When down-scale is enabled ( field in the Control 0 Register (Table 175 p. 132)), this bit must be programmed to 1. Defines the Alpha Blending value when is set to the following values: 001 = ARGB 1555, bit [0] is used as Alpha value 100 = aRGB 4444, bit [3:0[are used as Alpha value
28
PWRDNEN
RW 0x1
27
FRMNUMSEL
RW 0x0
26:25
DMABRSTSEL
RW( 0x0
24
YUV420SEL
RW( 0x0
23:20
RGBALPHA
RW 0x0
Copyright (c) 2007 Marvell July 17, 2007, Preliminary Document Classification: Proprietary Information
Doc. No. MV-S103921-00 Rev. - Page 135
88ALP01 Datasheet
Table 176: Control 1 Register (Continued)
Offset: 0x40
B its 19 F ie l d VCLKG Ty p e / I n it Va l RW 0x0 D e s c r i p t io n Internal vclk gating control (test only) 0 = internal vclk is always free running (Default) 1 = internal vclk is gated during horizontal and vertical blanking Reserved for future use Gamma Correction Reserved Shading Correction Reserved Reserved for future use
18 17 16 15:0
Reserved GCEN SCEN Reserved
RW RW 0x0 RW 0x0 RSVD
Table 177: Clock Control Register
Offset: 0x88
B its 31 30:29 F ie l d Reserved INTPIXCLKSEL Ty p e / I n it Va l RW 0x0 RW 0x0 D e s c r i p t io n Reserved Internal PIXCLK Select 00 = PIXMCLK 01 = PIXCLK 10 = PCI Clock 11 = Core clock Reserved Clock Fine Tune NOTE: Suppose the desired PIXMCLK frequency = FREQ. Program CLKDIV and CLKFT such that: CLKDIV = floor(core clock / FREQ) CLKFT = [((core clock/CLKDIV) - FREQ)/(core clock/CLKDIV)] * 0xFFF For example: When the clock source is 48 MHz and the sensor requires 8 MHz clock: set = 0x0006 and = 0x000 When the clock source is 48 MHz and the sensor requires 10 MHz clock: set = 0x0004 and = 0x2AB
28 27:16
Reserved CLKFT
RW 0x0 RW 0x0
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Copyright (c) 2007 Marvell July 17, 2007, Preliminary
Register Description
CMOS Camera Interface Controller
Table 177: Clock Control Register (Continued)
Offset: 0x88
B its 15:0 F ie l d CLKDIV Ty p e / I n it Va l RW 0x0 D e s c r i p t io n Clock Divider Value for PIXMCLK 0 = PIXMCLK is gated (no clock) Other = PIXMCLK is core clock divided by CLKDIV and CLKFT NOTE: Suppose the desired PIXMCLK frequency = FREQ. Program CLKDIV and CLKFT such that: CLKDIV = floor(core clock / FREQ) CLKFT = [((core clock/CLKDIV) - FREQ)/(core clock/CLKDIV)] * 0xFFF For example: When the clock source is 48 MHz and the sensor requires 8 MHz clock: set = 0x0006 and = 0x000 When the clock source is 48 MHz and the sensor requires 10 MHz clock: set = 0x0004 and = 0x2AB
Table 178: SRAM TC0 Register (Test Only)
Offset: 0x8C
B its 31:0 F ie l d SRAMTC0 Ty p e / I n it Va l RW 0x0 D e s c r i p t io n SRAM Timing Control 0
Table 179: SRAM TC1 Register (Test Only)
Offset: 0x90
B its 31:0 F ie l d SRAMTC1 Ty p e / I n it Va l RW 0x0 D e s c r i p t io n SRAM Timing Control 1
Table 180: General Purpose (GPR) Register
Offset: 0xB4
B its 15:6 5 F ie l d Reserved CTL1PADEN Ty p e / I n it Va l RSVD RW 0x0 D e s c r i p t io n Reserved SENSOR_CTL1 Pad Enable 0 = SENSOR_CTL1 Pad is tristated 1 = CTL1 drives SENSOR_CTL1 Pad
Copyright (c) 2007 Marvell July 17, 2007, Preliminary Document Classification: Proprietary Information
Doc. No. MV-S103921-00 Rev. - Page 137
88ALP01 Datasheet
Table 180: General Purpose (GPR) Register (Continued)
Offset: 0xB4
B its 4 F ie l d CTL0PADEN Ty p e / I n it Va l RW 0x0 RSVD RW 0x0 RW 0x0 D e s c r i p t io n SENSOR_CTL0 Pad Enable 0 = SENSOR_CTL0 Pad is tristated 1 = CTL0 drives SENSOR_CTL0 Pad Reserved Sensor Control 1 Controls SENSOR_CTL1 Pad. Sensor Control 0 Controls SENSOR_CTL0 Pad.
3:2 1 0
Reserved CTL1 CTL0
Table 181: TWSI Control 0 Register
Offset: 0xB8
B its 31:25 24 F ie l d Reserved TWSI_DRIVE_S EL Ty p e / I n it Va l RO 0x0 RW 0x0 D e s c r i p t io n Reserved Select the way TWSI_SDATA pad is driven. 0 = CCIC drives pad enable only 1 = CCIC drives both pad enable and pad input In both cases, external resistor pull-up is required. Insert Stop before re-start during TWSI read access This bit must be set when using Omnivision sensor. 0 = No Stop before re-start during read access 1 = Stop is inserted before re-start during read access TWSI Acknowledge Mask When enabled, allow CCIC's TWSI controller to ignore the Ack bit driven by the TWSI slave. 0 = Ack from slave is not masked 1 = Ack from slave is masked TWSI Software Mode Data When = 1, this bit controls TWSI_SDATA PAD. TWSI Software Mode CLK When = 1, this bit controls TWSI_SCLK PAD. TWSI Software Mode Enable 0 = Hardware mode 1 = TWSI PADs (TWSI_SCLK and TWSI_SDATA) are controlled by TWSI_SWMD_CLK and TWSI_SWMD_DTA Defines the divider value for TWSI_SCLK TWSI_SCLK frequency = PCI Clock / (4*(TWSICLKDIV+1))
23
TWSI_RDSTP
RW 0x0
22
TWSI_MASKACK RW 0x0
21
TWSI_SWMD_D RW TA 0x1 TWSI_SWMD_C RW LK 0x1 TWSI_SWMD_E N RW 0x0
20
19
18:10
TWSICLKDIV
RW 0x0
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Copyright (c) 2007 Marvell July 17, 2007, Preliminary
Register Description
CMOS Camera Interface Controller
Table 181: TWSI Control 0 Register (Continued)
Offset: 0xB8
B its 9:2 1 F ie l d TWSIID TWSIMODE Ty p e / I n it Va l RW 0x0 RW 0x0 RW 0x0 D e s c r i p t io n Slave ID Register TWSI Mode 0 = 8-bit (Default) 1 = 16-bit TWSI Enable 0 = Disable (Default) 1 = Enable
0
TWSIEN
Table 182: TWSI Control 1 Register
Offset: 0xBC
B its 31:28 27 F ie l d Reserved TWSIERR Ty p e / I n it Va l RO 0x0 RW 0x0 D e s c r i p t io n Reserved TWSI Error indication, due to NACK by CMOS sensor 0 = No error (Default) 1 = Error Write 0 to clear. 0 = Read data (bit [15:0]) is not ready (Default) 1 = Read data (bit [15:0]) is ready TWSIRVLD is immediately reset to 0 following a write to this register. 0 = No write or write is done (Default) 1 = Write is in progress. TWSIWSTAT is immediately set to 1 following a write to this register with = 0. 0 = Write (Default) 1 = Read TWSI Address A write to this register triggers TWSI access
26
TWSIRVLD
RO 0x0
25
TWSIWSTAT
RO 0x0
24 23:16 15:0
TWSIRnW TWSIADDR TWSIDATA
RW 0x0 RW 0x0 RW 0x0
Copyright (c) 2007 Marvell July 17, 2007, Preliminary Document Classification: Proprietary Information
Doc. No. MV-S103921-00 Rev. - Page 139
Figure 21: 128-pin TQFP Mechanical Drawing
4
D
1 4 2
97
PIN 1 IDENTIFIER
D1
O2 (4X) O 1
Symbol
96
128
Copyright (c) 2007 Marvell
July 17, 2007, Preliminary
1
R1
0.006 0.039 0.007 0.006 0.008 0.630 0.630 BSC 0.551 BSC 0.630 BSC 0.551 BSC 0.016 BSC 0.75 0.018 0.024 0.039 REF 0.20 3.5 7 13 13 0.003 0.003 0.008 0 0 11 11 12 12 11 11 12 12 13 13 3.5 7 0.008 0.030 0.007 0.009 0.041
Dimension in mm Min Nom Max 1.20 0.05 0.95 1.00 0.18 0.16 0.004 0.004 0.16 0.005 0.19 0.20 0.23 0.005 0.002 0.037 0.13 0.13 0.09 0.09 16.00 BSC 14.00 BSC 16.00 BSC 14.00 BSC 0.40 BSC 0.45 0.60 1.00 REF 0.08 0.08 0.20 0 0 0.15 1.05
Dimension in inch Min Nom Max 0.047
B
R2
GAGE PLANE
.25
E2 E1
2 1
E
B
S O3 L1 L
O
32 64
65
DETAIL "A"
33
D2
WITH PLATING
b
5 3
A A2
-C-
"A"
c
5 5
c1 b1
5
6
A1 b
BASE METAL
0.08 C
e
SECTION B-B
A A1 A2 b b1 c c1 D D1 E E1 e L L1 R1 R2 S O O1 O2 O3
Mechanical Drawings
Document Classification: Proprietary Information
Symbol D 2 E2
NOTE :
Die Pad Size Dimension in mm Dimension in inch 3.81 BSC .150 BSC 3.81 BSC .150 BSC
1. TO BE DETERMINED AT SEATING PLANE -C- . 2. DIMENSIONS D 1 AND E 1 DO NOT INCLUDE MOLD PROTRUSION . D1 AND E 1 ARE MAXIMUM PLASTIC BODY SIZE DIMENSIONS INCLUDING MOLD MISMATCH . 3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION . DAMBAR CAN NOT BE LOCATED ON THE LOWER RADIUS OF THE FOOT 4. EXACT SHAPE OF EACH CORNER IS OPTIONAL . 5. THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10 mm AND 0.25 mm FROM THE LEAD TIP . 6. A1 IS DEFINED AS THE DISTANCE FROM THE SEATING PLANE TO THE LOWEST POINT OF THE PACKAGE BODY . 7. CONTROLLING DIMENSION : MILLIMETER . .
Mechanical Drawings
Doc. No. MV-S103921-00 Rev. -
Note
All dimensions in mm. See Section 6, Part Order Numbering/Package Marking, on page 156 for package marking information and pin 1 location on package.
Page 140
Electrical Specifications
Absolute Maximum Ratings
5
5.1
Electrical Specifications
Absolute Maximum Ratings
Table 183: Absolute Maximum Ratings
S y m b ol VDD1 Parameter Power supply voltage with respect to VSS 88ALP01 pins: VDD Power supply voltage with respect to VSS 88ALP01 pins: VDDO Power supply voltage with respect to VSS 88ALP01 pins: VDDOC Storage temperature Min -0.5 Ty p 1.2 Max +1.5 or VDDO+0.5, whichever is less +4.0 U n i ts V
VDDO
-0.5
3.3
V
VDDOC
-0.5
2.5 to 3.3
+4.0
V
TSTORAGE
-55
--
+125
C
1. VDD must never be more than 0.5V greater than VDDO or damage results. This implies that power must be applied to VDDO before or at the same time as VDD.
5.2
Recommended Operating Conditions
Table 184: Recommended Operating Conditions
S y m b ol AVDD_PLL TA TJ VDD VDDO VDDOC P a r a m e te r 3.3V PLL Power Ambient operating temperature Maximum junction temperature Core power supply 3.3V digital I/O power supply Digital 2.5 to 3.3V power supply for camera interface VDDO C on d it io n Min 3.14 0 -1.14 3.14 2.38 Ty p 3.3 --1.20 3.3 2.5 to 3.3 Max 3.46 70 125 1.26 3.46 3.46 U n i ts V C C V V V
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Doc. No. MV-S103921-00 Rev. - Page 141
88ALP01 Datasheet
5.3
Package Thermal Conditions
Table 185: 14 x 14 mm TQFP Package
S y m b ol JA P a r a m e te r Thermal resistance. Junction to ambient of device package. JA = (TJ - TA)/ P P = total power dissipation C o n di ti on M in Ty p 32.60 Max -U ni ts C/W
Joint Electronic Device Engineering -Council (JEDEC) 3 in. x 4.5 in. 4-layer Printed Circuit Board (PCB) with no air flow JEDEC 3 in. x 4.5 in. 4-layer PCB with 1 m/s air flow JEDEC 3 in. x 4.5 in. 4-layer PCB with 2 m/s air flow JEDEC 3 in. x 4.5 in. 4-layer PCB with 3 m/s air flow ---------
29.50 28.40 27.80 0.24 0.44 0.56 0.65 12.40
---------
C/W C/W C/W C/W C/W C/W C/W C/W
JT
Thermal characteristic parameter. Junction to ambient of device package. JT = (TJ - TTOP)/P TTOP = temperature on top center of package P = total power dissipation
JEDEC 3 in. x 4.5 in. 4-layer PCB with no air flow JEDEC 3 in. x 4.5 in. 4-layer PCB with 1 m/s air flow JEDEC 3 in. x 4.5 in. 4-layer PCB with 2 m/s air flow JEDEC 3 in. x 4.5 in. 4-layer PCB with 3 m/s air flow
JC
JEDEC with no air flow Thermal resistance. Junction to ambient of device package. JC = (TJ - TC)/ PTOP PTOP = power dissipation from top of package Thermal resistance. Junction to ambient of device package. JB = (TJ - TB)/ PBOTTOM PBOTTOM = power dissipation from bottom of package to PCB surface JEDEC with no air flow
JB
--
23.10
--
C/W
5.4
5.4.1
DC Electrical Characteristics
Current Consumption AVDD_PLL
Table 186: Current Consumption AVDD_PLL
Over full range of values listed in the Recommended Operating Conditions unless otherwise specified. S y m b ol IAVDD_PLL P a r a m e te r 3.3V power to analog PLL P in s AVDD_PLL C on d it io n Min -Ty p 1 Max -U ni ts mA
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Copyright (c) 2007 Marvell July 17, 2007, Preliminary
Electrical Specifications
Input Clock Specifications
5.4.2
Current Consumption VDD
Table 187: Current Consumption VDD
Over full range of values listed in the Recommended Operating Conditions unless otherwise specified. S y m b ol IVDD P a r a m e te r Core power (1.2V) P in s VDD C on d it io n Min -Ty p 50 Max -U ni ts mA
5.4.3
Current Consumption VDDO
Table 188: Current Consumption VDDO
Over full range of values listed in the Recommended Operating Conditions unless otherwise specified. S y m b ol IVDDO P a r a m e te r I/O power (3.3V) P in s VDDO C on d it io n Min -Ty p 20 Max -U ni ts mA
5.4.4
Current Consumption VDDOC
Table 189: Current Consumption VDDOC
Over full range of values listed in the Recommended Operating Conditions unless otherwise specified. S y m b ol IVDDOC P a r a m e te r P in s C on d it io n Min -Ty p 4 Max -U ni ts mA
VDDOC I/O power for camera interface (2.5 to 3.3V)
5.5
Input Clock Specifications
Table 190: 24 MHz Reference Clock Timing
Over full range of values specified in the Recommended Operating Conditions unless otherwise specified. Sy m b o l TP_REF_CLK TH_REF_CLK TL_REF_CLK TR_REF_CLK TR_REF_CLK TF_REF_CLK P a r a m e te r REF_CLK period REF_CLK high time REF_CLK low time REF_CLK rise time REF_CLK rise time REF_CLK fall time
Condition
Min
41.667 - 50 ppm 18.75 18.75 ----
Ty p
41.667 20.833 20.833 ----
Max
41.667 + 25 ppm 22.917 22.917 3 5 3
U ni ts
ns ns ns ns ns ns
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Doc. No. MV-S103921-00 Rev. - Page 143
88ALP01 Datasheet
5.6
Internal Resistors
Table 191: Internal Resistors
R e si s to r Str e ng th NAND Flash 800 k Internal pull-up NF_ALE NF_CEn[1:0] NF_CLE NF_WEn NF_IO[7:0] NF_RDY NF_REn NF_WPn VPD TWSI 100 k Internal pull-up VPD_CLK VPD_DATA 10 9 50 48, 52 51 49 36, 31, 38, 39, 40, 41, 42, 46 54 53 47 Pi n N am e Pi n #
5.7
5.7.1
PCI Bus Interface Unit
DC Electricals
Table 192: PCI Bus Interface Unit DC Specifications
Over full range of values specified in the Recommended Operating Conditions unless otherwise specified. S y m b ol CCLK CIDSEL CIN IIL IOFF VIH VIL VIPU VOH VOL P a r a m e te r CLK pin capacitance IDSEL pin capacitance Input pin capacitance Input leakage current PMEn input leakage Input high voltage Input low voltage Input pull-up voltage Output high voltage Output low voltage IOUT = -500 A IOUT = 1500 A 0 < VIH < VDDO C o n di ti o n M in 5 ---Ty p ----------Max 12 8 10 10 1 U n i ts pF pF pF A A
VDDO 3.6V, VDDO -off or floating 0.5VDDO -0.5 0.7VDDO 0.9VDDO --
VDDO+0.5 V 0.3VDDO --0.1VDDO V V V V
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Electrical Specifications
PCI Bus Interface Unit
5.7.2
AC Electricals
Table 193: PCI Bus Interface Unit AC Specifications
Over full range of values specified in the Recommended Operating Conditions unless otherwise specified. S y m b ol ICH ICL IOH (AC) Parameter High clamp current Low clamp current Switching current high C o n di ti o n VDDO + 4 > VIN VDDO + 1 -3 < VIN -1 0 < VOUT 0.3VDDO Min Ty p Max ----1
U ni ts mA mA mA mA
25+(VIN-VDDO- -1)/0.015 +25+(VIN+1)/0. -015 -12VDDO ----16VDDO ----1 1 ---
0.3VDDO < VOUT < -17.1 0.9VDDO (VDDO-VOUT) 0.7VDDO < VOUT < VDDO (Test point) IOL(AC) Switching current low VOUT = 0.7VDDO VDDO > VOUT 0.6VDDO
-32VDDO --2
mA mA mA
0.6VDDO > VOUT > 26.7VOUT 0.1VDDO 0.18VDDO > VOUT >0 (Test point) TSLEW_FALL TSLEW_RISE Output fall slew rate VOUT = 0.18VDDO 0.6VDDO 0.2VDDOI load
38VDDO 4 4
mA V/ns V/ns
Output rise slew 0.2VDDO rate 0.6VDDO load
1. IOH = (0.98/VDDO) * (VOUT - VDDO) * (VOUT + 0.4VDDO) for VDDO > VOUT > 0.7VDDO 2. IOL = (256/VDDO) * VOUT * (VDDO - VOUT) for 0V < VOUT < 0.18VDDO
5.7.3
Protocol Timing
Table 194: 66 and 33 MHz PCI Timing
Over full range of values specified in the Recommended Operating Conditions unless otherwise specified. S y m b ol P a r a m e te r PCI 66 M in TH TOFF TON Input hold time from CLK Active to float delay Float to active delay 0 -2 Max -14 -PCI 33 M in 0 -2 Max -28 -ns ns ns U n i ts
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88ALP01 Datasheet
Table 194: 66 and 33 MHz PCI Timing (Continued)
Over full range of values specified in the Recommended Operating Conditions unless otherwise specified. S y m b ol P a r a m e te r PCI 66 M in TRHFA TRHFF TRST TRST_CLK TRST_OFF TSU TSU(PTP) TVAL TVAL(PTP) RSTn high to first configuration access RSTn high to first FRAMEn assertion Reset active time after power stable Reset active time after CLK stable Reset active to output float delay Input setup time to CLK-bused signals Input setup time to CLK-point to point signals CLK to signal valid delay-bused signals CLK to signal valid delay-point to point signals 225 5 1 100 -3 5 2 2 Max ----40 --6 6 PCI 33 M in 225 5 1 100 -7 10, 12 2 2 Max ----40 --11 12 clocks clocks ns ns ns ns ns ns ns U n i ts
5.8
5.8.1
NAND Flash Controller
DC Electricals
Table 195: NAND Flash DC Specifications
Over full range of values specified in the Recommended Operating Conditions unless otherwise specified. S y m b ol VIH VIL VOH VOL P a r a m e te r Input high voltage Input low voltage Output high voltage Output low voltage C o nd i tio n M in ----Ty p 2.6 0.6 2.4 0.4 Max ----U n i ts V V V V
5.8.2
Protocol Timing
The following NAND Flash Controller timing parameters are achieved by setting: Note Timing Parameter Register 1 (Table 96 p. 95) to 0x10100900 Timing Parameter Register 2 (Table 97 p. 96) to 0x00010102 Timing Parameter Register 3 (Table 98 p. 96) to 0x10000000
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Electrical Specifications
NAND Flash Controller
Figure 22: NAND Flash Command Write
NF_CLE
TCLS
TCLH
NF_CE[1:0]n
T CS
NF_WEn
NF_IO[7:0]
NF_REn
TCEA
NAND Flash Clock
Figure 23: NAND Flash Address Write
NF_ALE
T ALS
TALH
NF_WEn
NF_IO[7:0]
NF_REn
NAND Flash Clock
Copyright (c) 2007 Marvell July 17, 2007, Preliminary Document Classification: Proprietary Information
~
~
~
~
~
TAR
~
~
~
~
TWHR
~
~
TCLR
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88ALP01 Datasheet
Figure 24: NAND Flash Data Write
TADL
NF_CLE
TWC
NF_WEn
T WP
T WH
NF_IO[7:0]
Last Address Byte T DS
1 Data Byte TDH
st
NAND Flash Clock
Figure 25: NAND Flash Data Read
NF_WEn TWB
NF_RDY
T IR
TRC
NF_REn
T RP
TRH
NF Data In TREA
Data TROH
NAND Flash Clock
Table 196: NAND Flash Timing
S y m b ol TADL Parameter Address to data loading time Note M in Ty p -Max -U n i ts ns
104 Requires one dummy address cycle 10.4 20.8 104 -10.4
TALH TALS TAR TCEA TCLH
NF_ALE hold time NF_ALE setup time NF_ALE to NF_REn delay NF_CE access time NF_CLE hold time
------
---260 --
ns ns ns ns ns
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Electrical Specifications
SDIO
Table 196: NAND Flash Timing (Continued)
S y m b ol TCLR TCLS TCS TDH TDS TRC TREA TRP TRR TWB TWC TWH TWHR TWP Parameter NF_CLE to NF_REn delay NF_CLE setup time NF_CE setup time Data hold time Data setup time Read cycle time NF_REn access time NF_REn pulse width Ready to NF_REn low NF_WEn high to busy Write cycle time NF_WEn high hold time NF_WEn high to NF_REn low NF_WEn pulse width Note M in 135 52 52 10.4 20.8 31.2 Max tolerable -delay = 25.5 ns 20.8 31.2 -41.6 10.4 104 31.2 Ty p --------------Max ------25 --104 ----U n i ts ns ns ns ns ns ns ns ns ns ns ns ns ns ns
5.9
5.9.1
SDIO
DC Electricals
Table 197: SDIO DC Specifications
Over full range of values specified in the Recommended Operating Conditions unless otherwise specified. S y m b ol VIH VIL VOH VOL P a r a m e te r Input high voltage Input low voltage Output high voltage Output low voltage IOH = -100 A @ VDD min C o nd i tio n M in 0.625 * VDD VSS - 0.3 0.75 * VDD Ty p ----Max VDD + 0.3 0.25 * VDD -0.125 * VDD U n i ts V V V V
IOL = 100 A @ -VDD min
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88ALP01 Datasheet
5.9.2
Protocol Timing
Figure 26: SDIO Low Speed Timing Diagram
fPP TWL TWH TISU Clock TTHL TISU Input TODLY (max) Output TODLY (min) TTLH TIH
Table 198: SDIO Low Speed Timing
Over full range of values specified in the Recommended Operating Conditions unless otherwise specified. All clock values are referred to min (VIH) and max (VIL). All inputs and outputs are referenced to clock. S y m b ol fOD P a r a m e te r Clock frequency identification mode (low requency is required for MMC capability) Clock frequency data transfer mode Input hold time Input setup time Output delay time during data transfer mode Output delay time during identification mode Clock fall time Clock fall time Clock rise time Clock rise time Clock high time Clock high time C o nd i tio n Min Ty p Max 400 U n i ts kHz
0/100 kHz --
fPP TIH TISU TODLY TODLY TTHL TTHL TTLH TTLH TWH TWH
0 5 5.83 --CL <=100 pF -(7 cards) -CL <=250 pF -(21 cards) CL <=100 pF -(7 cards) CL <=100 pF 10 (7 cards) CL <=250 pF 50 (21 cards)
------------
24 --14 50 10 50 10 50 ---
MHz ns ns ns ns ns ns ns ns ns ns
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Electrical Specifications
SDIO
Table 198: SDIO Low Speed Timing (Continued)
Over full range of values specified in the Recommended Operating Conditions unless otherwise specified. All clock values are referred to min (VIH) and max (VIL). All inputs and outputs are referenced to clock. S y m b ol TWL TWL P a r a m e te r Clock low time Clock low time C o nd i tio n Min Ty p --Max --U n i ts ns ns
CL <=100 pF 10 (7 cards) CL <=250 pF 50 (21 cards)
Figure 27: SDIO High Speed Timing Diagram
fPP TWL Clock TTHL Input TISU T TLH TIH TWH
VIH VIL VIH VIL
Output TODLY TOH
VOH VOL
Table 199: SDIO High Speed Timing
Over full range of values specified in the Recommended Operating Conditions unless otherwise specified. All clock values are referred to min (VIH) and max (VIL). All inputs and outputs are referenced to clock. S y m b ol fPP TIH TISU TODLY TOH TTHL TTLH TWH TWL Parameter Clock frequency data transfer mode Input hold time Input setup time Output delay time during data transfer mode Output hold time Clock fall time Clock rise time Clock high time Clock low time C o n d iti o n M in 0 2 6.83 -2.5 --7 7 Ty p ---------Max 48 --14 -3 3 --U n i ts MHz ns ns ns ns ns ns ns ns
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88ALP01 Datasheet
5.10
5.10.1
CMOS Camera Interface
DC Electricals
Table 200: CMOS Camera Interface DC Specifications
Over full range of values specified in the Recommended Operating Conditions unless otherwise specified. S y m b ol VDD_IO VIH VIL VOH VOL P a r a m e te r DC supply voltage-I/O power Input high voltage Input low voltage Output high voltage Output low voltage 8 mA C o nd i tio n M in 2.5 0.7*VDD_IO -0.9*VDD_IO -Ty p -----Max 3.3 -0.3*VDD_IO -0.1*VDD_IO U n i ts V V V V V
5.10.2
Protocol Timing
Figure 28: CMOS Camera Interface TWSI Timing Diagram
TF TWSI_SCLK TSU_STA TLOW T HIGH TR
T HD_STA
T HD_DAT
TSU_DAT
TSU_STO
TWSI_SDATA TAA TAA
Figure 29: CMOS Camera Interface Timing Diagram
TPCLK PIXCLK TSU HSYNC VSYNC PIXDATA[7:0] THD
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Electrical Specifications
JTAG Test Interface
Table 201: CMOS Camera Timing
Over full range of values specified in the Recommended Operating Conditions unless otherwise specified. S y m b ol TAA TDH THD THD_DAT THD_STA THIGH TLOW TPIXCLK TPIXMCLK P a r a m e te r Clock low to data out valid Data out hold time Hold time Data in hold time Start condition hold time Clock high period Clock low period Input pixel clock Output clock frequency C o n di ti o n Min --4 --0.13 0.13 -Ty p 0.25 0.25 -0.25 0.25 Max -----U n i ts clock period clock period ns clock period clock period s s MHz MHz ns ns clock period clock period clock period MHz
Programmable -Programmable --48 48 3 -----
Programmable --4 ------0.25 0.25 0.25
TRISE_FALL Rise/fall times TSU TSU_DAT TSU_STA TSU_STO Setup time Data in setup time Start condition setup time Stop condition setup time
TTWSI_SCLK Clock frequency
Programmable 41
1. Clock controlled by TWSI Control 0 Register (Table 181 p. 138). Maximum TWSI clock is 4 MHz if PCI bus clock is 33 MHz.
5.11
5.11.1
JTAG Test Interface
DC Electricals
Table 202: JTAG Test Interface DC Specifications for 3.3V Signaling
Over full range of values specified in the Recommended Operating Conditions unless otherwise specified. S y m b ol VOH VOL P a r a m e te r Output high voltage Output low voltage C on d it io n 4 mA 4 mA M in 2.4 -Ty p --Max -0.4 U n i ts V V
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88ALP01 Datasheet
Table 202: JTAG Test Interface DC Specifications for 3.3V Signaling (Continued)
Over full range of values specified in the Recommended Operating Conditions unless otherwise specified. S y m b ol VIH VIL P a r a m e te r Input high voltage Input low voltage C on d it io n --M in 0.6*VDDO -0.4 Ty p --Max U n i ts
VDDO+0.4 V 0.3*VDDO V
5.11.2
Protocol Timing
Figure 30: JTAG Timing Diagram
TESTMODE TP_TCK TL_TCK TCK T SU_TDI TDI TMS TDLY_TDO TDO THD_TDI TH_TCK
Table 203: JTAG Timing
Over full range of values specified in the Recommended Operating Conditions unless otherwise specified. S y m b ol TDLY_TDO TH_TCK THD_TDI TL_TCK TP_TCK TSU_TDI Parameter TCK to TDO Delay TCK High TDI, TMS to TCK Hold Time TCK Low TCK Period TDI, TMS to TCK Setup Time C o nd i tio n ------Min 0 12 10 12 40 10 Ty p ------Max 15 -----U ni ts ns ns ns ns ns ns
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Copyright (c) 2007 Marvell July 17, 2007, Preliminary
Electrical Specifications
GPIO
5.12
5.12.1
GPIO
DC Electricals
Table 204: GPIO DC Specifications for 3.3V Signaling
Over full range of values specified in the Recommended Operating Conditions unless otherwise specified. S y m b ol VIH VIL VOH VOL P a r a m e te r Input high voltage Input low voltage Output high voltage Output low voltage C o nd i tio n --When Iout = 8 mA When Iout = 8 mA Min 0.6*VDDO -0.4 2.4 -Ty p ----Max U n i ts
VDDO+0.4 V 0.3*VDDO -0.4 V V V
5.12.2
LED Mode
Table 205: LED Mode1
Over full range of values specified in the Recommended Operating Conditions unless otherwise specified. S y m b ol IOH IOL P a r a m e te r C o nd i tio n Min 25.0 25.0 Ty p --Max --U n i ts mA mA
Switching current high VDDO-0.4 Switching current low 0.4
1. LED Mode is independently selectable for each GPIO pin.
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Doc. No. MV-S103921-00 Rev. - Page 155
88ALP01 Datasheet
6
6.1
Part Order Numbering/Package Marking
Part Order Numbering
Figure 31 shows the part order numbering scheme for the 88ALP01. Refer to Marvell Field Application Engineers (FAEs) or representatives for further information when ordering parts.
Figure 31: Sample Part Number
88ALP01 -xx-xxx-C000-xxxx
Custom code (optional)
Part number
Custom code
Temperature code C = Commercial I = Industrial Custom code Custom code Environmental code + = RoHS 0/6 - = RoHS 5/6 1 = RoHS 6/6
Package code TFJ = 128-pin TQFP
r
Table 206: 88ALP01 Part Order Options
P a c k a g e Ty p e 128-pin TQFP with EPAD Part Order Number 88ALP01-xx-TFJ1C000 (RoHS 6/6 compliant package)
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Copyright (c) 2007 Marvell July 17, 2007, Preliminary
Part Order Numbering/Package Marking
Package Marking
6.2
Package Marking
Figure 32 shows a sample Commercial package marking and pin 1 location for the 88ALP01.
Figure 32: Commercial Package Marking and Pin 1 Location
Marvell logo
Country of origin
(Contained in the mold ID or marked as the last line on the package.)
88ALP01-TFJe Lot Number YYWW xx@ Country of Origin
Part number, package code, environmental code
XXXX = Part number AAA = Package code e = Environmental code (+ = RoHS 0/6, no code = RoHS 5/6, 1 = RoHS 6/6)
Date code, custom code, assembly plant code Pin 1 location
YYWW = Date code (YY = year, WW = Work Week) xx = Custom code @ = Assembly plant code
Note: The above drawing is not drawn to scale. Location of markings is approximate.
Copyright (c) 2007 Marvell July 17, 2007, Preliminary Document Classification: Proprietary Information
Doc. No. MV-S103921-00 Rev. - Page 157
88ALP01 Datasheet
A
Acronyms and Abbreviations
Table 207: Acronyms and Abbreviations
Acronym BIU CCIC CRC DMA EAV ECR fOD JTAG MSB NFC PCI RCA SAV SDIO SPI TWSI VPD D e f in it io n Bus Interface Unit CMOS Camera Interface Controller Cyclic Redundancy Check Direct Memory Address End-of-Active-Video Engineering Change Request Open Drain frequency Joint Test Action Group Most Significant Bit NAND Flash Controller Peripheral Component Interconnect Relative Card Address Start-of-Active-Video Secure Digital Input/Output Serial Peripheral Interface Two-Wire Serial Interface Vital Product Data
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Acronyms and Abbreviations
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Doc. No. MV-S103921-00 Rev. - Page 159
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